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Revision 11
IGLOO PLUS Low Power Flash FPGAs
with Flash*Freeze Technology Features and Benefits
Low Power
* * * * * 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation 5 W Power Consumption in Flash*Freeze Mode Low Power Active FPGA Operation Flash*Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content * Configurable Hold Previous State, Tristate, HIGH, or LOW State per I/O in Flash*Freeze Mode * Easy Entry To / Exit From Ultra-Low Power Flash*Freeze Mode
(R)
Advanced I/O
* 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation * Bank-Selectable I/O Voltages--4 Banks per Chip on All IGLOO(R) PLUS Devices * Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V * Selectable Schmitt Trigger Inputs * Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V * Wide Range Power Supply Voltage Support per JESD8-12, Allowing I/Os to Operate from 1.14 V to 1.575 V * I/O Registers on Input, Output, and Enable Paths * Hot-Swappable and Cold-Sparing I/Os * Programmable Output Slew Rate and Drive Strength * Weak Pull-Up/-Down * IEEE 1149.1 (JTAG) Boundary Scan Test * Pin-Compatible Small-Footprint Packages across the IGLOO PLUS Family * Six CCC Blocks, One with an Integrated PLL * Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback * Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Feature Rich
* 30 k to 125 k System Gates * Up to 36 kbits of True Dual-Port SRAM * Up to 212 User I/Os
Reprogrammable Flash Technology
* * * * * 130-nm, 7-Layer Metal, Flash-Based CMOS Process Live-at-Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design When Powered Off 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance
Clock Conditioning Circuit (CCC) and PLL
In-System Programming (ISP) and Security
* Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532-compliant) * FlashLock(R) to Secure FPGA Contents
Embedded Memory
* 1 kbit of FlashROM User Nonvolatile Memory * SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (x1, x2, x4, x9, and x18 organizations) * True Dual-Port SRAM (except x18)
High-Performance Routing Hierarchy
* Segmented, Hierarchical Routing and Clock Structure
Table 1 * IGLOO PLUS Product Family IGLOO PLUS Devices System Gates Typical Equivalent Macrocells VersaTiles (D-flip-flops) Flash*Freeze Mode (typical, W) RAM Kbits (1,024 bits) 4,608-Bit Blocks Secure (AES) ISP FlashROM Kbits Integrated PLL in CCCs VersaNet Globals I/O Banks Maximum User I/Os Package Pins CS VQ
2 1
AGLP030 30,000 256 792 5 - - - 1 - 6 4 120 CS201, CS289 VQ128
AGLP060 60,000 512 1,584 10 18 4 Yes
1
AGLP125 125,000 1,024 3,120 16
36 8 Yes
1
1 18 4 212
1 18 4 157 CS201, CS289 VQ176
CS281, CS289
Notes: 1. AGLP060 in CS201 does not support the PLL. 2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125.
The AGLP030 device does not support this feature.
June 2010 (c) 2010 Actel Corporation I
IGLOO PLUS Low Power Flash FPGAs
I/Os Per Package 1
IGLOO PLUS Devices Package CS201 CS281 CS289 VQ128 VQ176 120 - 120 101 - AGLP030 AGLP060 Single-Ended I/Os 157 - 157 - 137 - 212 212 - - AGLP125
Note: When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of singleended user I/Os available is reduced by one. Table 2 * IGLOO PLUS FPGAs Package Size Dimensions Package Length x Width (mm/mm) Nominal Area (mm2) Pitch (mm) Height (mm) CS201 8x8 64 0.5 0.89 CS281 10 x 10 100 0.5 1.05 CS289 14 x 14 196 0.8 1.20 VQ128 14 x 14 196 0.4 1.0 VQ176 20 x 20 400 0.4 1.0
IGLOO PLUS Device Status
IGLOO PLUS Device AGLP030 AGLP060 AGLP125 Status Production Production Production
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IGLOO PLUS Low Power Flash FPGAs
IGLOO PLUS Ordering Information
AGLP125 V2 _ CS G 289 I Application (Temperature Range) Blank = Commercial (0C to +70C ambient temperature) I = Industrial (-40C to +85C ambient temperature) PP = Pre-Production ES = Engineering Sample (room temperature only) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G= RoHS-Compliant Packaging Package Type CS = Chip Scale Package (0.5 mm and 0.8 mm pitches) VQ = Very Thin Quad Flat Pack (0.4 mm pitch) Supply Voltage 2 = 1.2 V to 1.5 V 5 = 1.5 V only Part Number AGLP030 = 30,000 System Gates AGLP060 = 60,000 System Gates AGLP125 = 125,000 System Gates
Notes: 1. Marking information: IGLOO PLUS V2 devices do not have a V2 marking, but IGLOO PLUS V5 devices are marked accordingly. 2. "G" indicates RoHS-compliant packages.
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IGLOO PLUS Low Power Flash FPGAs
Temperature Grade Offerings
Package CS201 CS281 CS289 VQ128 VQ176 AGLP030 C, I - C, I C, I - AGLP060 C, I - C, I - C, I AGLP125 - C, I C, I - -
Notes: 1. C = Commercial temperature range: 0C to 70C ambient temperature. 2. I = Industrial temperature range: -40C to 85C ambient temperature. Contact your local Actel representative for device availability: http://www.actel.com/company/contact/default.aspx.
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Table of Contents
IGLOO PLUS Device Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
IGLOO PLUS DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57 Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61 Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64 Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-77 JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78 Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79
Package Pin Assignments
128-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 176-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 201-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 281-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 289-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
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1 - IGLOO PLUS Device Family Overview
General Description
The IGLOO PLUS family of flash FPGAs, based on a 130 nm flash process, offers the lowest power FPGA, a single-chip solution, small-footprint packages, reprogrammability, and an abundance of advanced features. The Flash*Freeze technology used in IGLOO PLUS devices enables entering and exiting an ultra-low power mode that consumes as little as 5 W while retaining the design information, SRAM content, registers, and I/O states. Flash*Freeze technology simplifies power management through I/O and clock management with rapid recovery to operation mode. The Low Power Active capability (static idle) allows for ultra-low power consumption while the IGLOO PLUS device is completely functional in the system. This allows the IGLOO PLUS device to control system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power. Nonvolatile flash technology gives IGLOO PLUS devices the advantage of being a secure, low power, single-chip solution that is live at power-up (LAPU). IGLOO PLUS is reprogrammable and offers time-tomarket benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. IGLOO PLUS devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). IGLOO PLUS devices have up to 125 k system gates, supported with up to 36 kbits of true dual-port SRAM and up to 212 user I/Os. The AGLP030 devices have no PLL or RAM support.
Flash*Freeze Technology
The IGLOO PLUS device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra-low power Flash*Freeze mode. IGLOO PLUS devices do not need additional components to turn off I/Os or clocks while retaining the design information, SRAM content, registers, and I/O states. Flash*Freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. The ability of IGLOO PLUS V2 devices to support a wide range of core and I/O voltages (1.2 V to 1.5 V) allows further reduction in power consumption, thus achieving the lowest total system power. During Flash*Freeze mode, each I/O can be set to the following configurations: hold previous state, tristate, or set as HIGH or LOW. The availability of low power modes, combined with reprogrammability, a single-chip and single-voltage solution, and availability of small-footprint, high-pin-count packages, make IGLOO PLUS devices the best fit for portable electronics.
Flash Advantages
Low Power
IGLOO PLUS devices exhibit power characteristics similar to those of an ASIC, making them an ideal choice for power-sensitive applications. IGLOO PLUS devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. IGLOO PLUS devices also have low dynamic power consumption to further maximize power savings; power is even further reduced by the use of a 1.2 V core voltage. Low dynamic power consumption, combined with low static power consumption and Flash*Freeze technology, gives the IGLOO PLUS device the lowest total system power offered by any FPGA.
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IGLOO PLUS Device Family Overview
Security
The nonvolatile, flash-based IGLOO PLUS devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. IGLOO PLUS devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. IGLOO PLUS devices (except AGLP030) utilize a 128-bit flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In addition, all FlashROM data in IGLOO PLUS devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. IGLOO PLUS devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. IGLOO PLUS devices with AES-based security allow for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed IGLOO PLUS device cannot be read back, although secure design verification is possible. Security, built into the FPGA fabric, is an inherent component of the IGLOO PLUS family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The IGLOO PLUS family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected and secure, making remote ISP possible. An IGLOO PLUS device provides the most impenetrable security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOO PLUS FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. The IGLOO PLUS devices can be operated with a 1.2 V or 1.5 V single-voltage supply for core and I/Os, eliminating the need for additional supplies while minimizing total power consumption.
Live at Power-Up
The Actel flash-based IGLOO PLUS devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based IGLOO PLUS devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system power will not corrupt the IGLOO PLUS device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based IGLOO PLUS devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. IGLOO PLUS flash FPGAs allow the user to quickly enter and exit Flash*Freeze mode. This is done almost instantly (within 1 s), and the device retains configuration and data in registers and RAM. Unlike SRAM-based FPGAs, the device does not need to reload configuration and design state from external memory components; instead, it retains all necessary information to resume operation immediately.
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAMbased FPGAs, flash-based IGLOO PLUS devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the
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IGLOO PLUS Low Power Flash FPGAs industry-standard AES algorithm. The IGLOO PLUS family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the IGLOO PLUS family a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/communications, computing, and avionics markets.
Firm-Error Immunity
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of IGLOO PLUS flashbased FPGAs. Once it is programmed, the flash cell configuration element of IGLOO PLUS FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric.
Advanced Flash Technology
The IGLOO PLUS family offers many benefits, including nonvolatility and reprogrammability, through an advanced flash-based, 130 nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. IGLOO PLUS family FPGAs utilize design and process techniques to minimize power consumption in all modes of operation.
Advanced Architecture
The proprietary IGLOO PLUS architecture provides granularity comparable to standard-cell ASICs. The IGLOO PLUS device consists of five distinct and programmable architectural features (Figure 1-1 on page 1-4): * * * * * * Flash*Freeze technology FPGA VersaTiles Dedicated FlashROM Dedicated SRAM/FIFO memory Extensive CCCs and PLLs Advanced I/O structure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the IGLOO PLUS core tile as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation-architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of IGLOO PLUS devices via an IEEE 1532 JTAG interface.
The AGLP030 device does not support PLL or SRAM.
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IGLOO PLUS Device Family Overview
Bank 0 * CCC
Bank 3
RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block*
Bank 1
I/Os
Bank 3
VersaTile
Bank 1
ISP AES Decryption*
User Nonvolatile FlashRom
Flash*Freeze Technology
Charge Pumps
Bank 2
* Not supported by AGLP030 devices Figure 1-1 * IGLOO PLUS Device Architecture Overview with Four I/O Banks (AGLP030, AGLP060, and AGLP125)
Flash*Freeze Technology
The IGLOO PLUS device has an ultra-low power static mode, called Flash*Freeze mode, which retains all SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology enables the user to quickly (within 1 s) enter and exit Flash*Freeze mode by activating the Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and global I/Os can still be driven and can be toggling without impact on power consumption, clocks can still be driven or can be toggling without impact on power consumption, and the device retains all core registers, SRAM information, and I/O states. I/Os can be individually configured to either hold their previous state or be tristated during Flash*Freeze mode. Alternatively, they can be set to a certain state using weak pullup or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL, and the device consumes as little as 5 W in this mode. Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying the power management of the device. The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide when it is safe to transition to this mode. Refer to Figure 1-2 for an illustration of entering/exiting Flash*Freeze mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode usage is not planned.
Flash*Freeze Mode Control
Actel IGLOO PLUS FPGA
Flash*Freeze Pin
Figure 1-2 *
IGLOO PLUS Flash*Freeze Mode
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VersaTiles
The IGLOO PLUS core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS(R) core tiles. The IGLOO PLUS VersaTile supports the following: * * * * All 3-input logic functions--LUT-3 equivalent Latch with clear or set D-flip-flop with clear or set Enable D-flip-flop with clear or set
Refer to Figure 1-3 for VersaTile configurations.
LUT-3 Equivalent X1 X2 X3
D-Flip-Flop with Clear or Set Data CLK CLR Y D-FF
Enable D-Flip-Flop with Clear or Set Data CLK Enable CLR D-FF Y
LUT-3
Y
Figure 1-3 *
VersaTile Configurations
User Nonvolatile FlashROM
Actel IGLOO PLUS devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: * * * * * * * * Internet protocol addressing (wireless or fixed) System calibration settings Device serialization and/or inventory control Subscription-based business models (for example, set-top boxes) Secure key storage for secure communications algorithms Asset management/tracking Date stamping Version management
The FlashROM is written using the standard IGLOO PLUS IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks (except in AGLP030 devices), as in security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The Actel IGLOO PLUS development software solutions, Libero(R) Integrated Design Environment (IDE) and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents.
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IGLOO PLUS Device Family Overview
SRAM and FIFO
IGLOO PLUS devices (except AGLP030 devices) have embedded SRAM blocks along their north side. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256x18, 512x9, 1kx4, 2kx2, and 4kx1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in AGLP030 devices). In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
IGLOO PLUS devices provide designers with very flexible clock conditioning circuit (CCC) capabilities. Each member of the IGLOO PLUS family contains six CCCs. One CCC (center west side) has a PLL. The AGLP030 device does not have a PLL or CCCs; it contains only inputs to six globals. The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC (center west side) has a PLL. The four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has these key features: * * * * * * * * * * Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz 2 programmable delay types for clock skew minimization Clock frequency synthesis (for PLL only) Internal phase shift = 0, 90, 180, and 270. Output phase shift depends on the output divider configuration (for PLL only). Output duty cycle = 50% 1.5% or better (for PLL only) Low output jitter: worst case < 2.5% x clock period peak-to-peak period jitter when single global network used (for PLL only) Maximum acquisition time is 300 s (for PLL only) Exceptional tolerance to input period jitter--allowable input jitter is up to 1.5 ns (for PLL only) Four precise phases; maximum misalignment between adjacent phases (for PLL only) is 40 ps x 250 MHz / fOUT_CCC
Additional CCC specifications:
Global Clocking
IGLOO PLUS devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets.
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IGLOO PLUS Low Power Flash FPGAs
I/Os with Advanced I/O Standards
The IGLOO PLUS family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). IGLOO PLUS FPGAs support many different I/O standards. The I/Os are organized into four banks. All devices in IGLOO PLUS have four banks. The configuration of these banks determines the I/O standards supported. Each I/O module contains several input, output, and output enable registers. Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a powered-up system. Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating.
Wide Range I/O Support
Actel IGLOO PLUS devices support JEDEC-defined wide range I/O operation. IGLOO PLUS devices support both the JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to 1.575 V. Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components with greater tolerances. Wide range eases I/O bank management and provides enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage applications.
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2 - IGLOO PLUS DC and Switching Characteristics
General Specifications
Operating Conditions
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 * Absolute Maximum Ratings Symbol VCC VJTAG VPUMP VCCPLL VCCI VI
1 2
Parameter DC core supply voltage JTAG DC voltage Programming voltage Analog power supply (PLL) DC I/O buffer supply voltage I/O input voltage Storage temperature Junction temperature
Limits -0.3 to 1.65 -0.3 to 3.75 -0.3 to 3.75 -0.3 to 1.65 -0.3 to 3.75 -0.3 V to 3.6 V -65 to +150 +125
Units V V V V V V C C
TSTG TJ 2
Notes:
1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3. 2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating limits, refer to Table 2-2 on page 2-2.
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IGLOO PLUS DC and Switching Characteristics Table 2-2 * Recommended Operating Conditions1,2 Symbol TA TJ VCC3 Ambient temperature Junction temperature2 1.5 V DC core supply voltage 4
5,6
Parameter
Commercial 0 to +70 0 to + 85 1.425 to 1.575 1.14 to 1.575 1.4 to 3.6
Industrial -40 to +85 -40 to +100 1.425 to 1.575 1.14 to 1.575 1.4 to 3.6 3.15 to 3.45 0 to 3.6 1.425 to 1.575 1.14 to 1.575 1.14 to 1.26 1.14 to 1.575 1.425 to 1.575 1.7 to 1.9 2.3 to 2.7 2.7 to 3.6 3.0 to 3.6
Units C C V V V V V V V V V V V V V V
1.2 V-1.5 V wide range core voltage VJTAG VPUMP7 JTAG DC voltage Programming voltage
Programming mode Operation
3.15 to 3.45 0 to 3.6
4
VCCPLL
8
Analog power supply (PLL)
1.5 V DC core supply voltage
1.425 to 1.575 1.14 to 1.575 1.14 to 1.26 1.14 to 1.575 1.425 to 1.575 1.7 to 1.9 2.3 to 2.7 2.7 to 3.6 3.0 to 3.6
1.2 V-1.5 V wide range core voltage5 VCCI 1.2 V DC supply voltage5 1.2 V DC wide range supply voltage5 1.5 V DC supply voltage 1.8 V DC supply voltage 2.5 V DC supply voltage 3.3 V wide range DC supply voltage9 3.3 V DC supply voltage Notes:
1. All parameters representing voltages are measured with respect to GND unless otherwise specified. 2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel recommends that the user follow best design practices using Actel's timing and power simulation tools. 3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-21 on page 2-19. VCCI should be at the same voltage within a given I/O bank. 4. For IGLOO(R) PLUS V5 devices 5. For IGLOO PLUS V2 devices only, operating at VCCI VCC. 6. All IGLOO PLUS devices (V5 and V2) must be programmed with the VCC core voltage at 1.5 V. Applications using V2 devices powered by a 1.2 V supply must switch the core supply to 1.5 V for in-system programming. 7. VPUMP can be left floating during operation (not programming mode). 8. VCCPLL pins should be tied to VCC pins. See the Pin Descriptions chapter of the IGLOO PLUS FPGA Fabric User's Guide for further information. 9. 3.3 V wide range is compliant to the JDEC8b specification and supports 3.0 V VCCI operation.
Table 2-3 * Flash Programming Limits - Retention, Storage, and Operating Temperature 1 Product Grade Commercial Industrial Notes:
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits.
Programming Cycles 500 500
Program Retention (biased/unbiased) 20 years 20 years
Maximum Storage Temperature TSTG (C) 2 110 110
Maximum Operating Junction Temperature TJ (C) 2 100 100
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IGLOO PLUS Low Power Flash FPGAs Table 2-4 * Overshoot and Undershoot Limits 1 Average VCCI-GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle2 10% 5% 3V 3.3 V 3.6 V Notes:
1. Based on reliability requirements at 85C. 2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.
VCCI 2.7 V or less
Maximum Overshoot/ Undershoot2 1.4 V 1.49 V 1.1 V 1.19 V 0.79 V 0.88 V 0.45 V 0.54 V
10% 5% 10% 5% 10% 5%
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every IGLOO PLUS device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1 on page 2-4. There are five regions to consider during power-up. IGLOO PLUS I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 and Figure 2-2 on page 2-5). 2. VCCI > VCC - 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up (V5 devices): 0.6 V < trip_point_up < 1.2 V Ramping down (V5 devices): 0.5 V < trip_point_down < 1.1 V Ramping up (V2 devices): 0.75 V < trip_point_up < 1.05 V Ramping down (V2 devices): 0.65 V < trip_point_down < 0.95 V VCC Trip Point: Ramping up (V5 devices): 0.6 V < trip_point_up < 1.1 V Ramping down (V5 devices): 0.5 V < trip_point_down < 1.0 V Ramping up (V2 devices): 0.65 V < trip_point_up < 1.05 V Ramping down (V2 devices): 0.55 V < trip_point_down < 0.95 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: * * During programming, I/Os become tristated and weakly pulled up to VCCI. JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior.
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IGLOO PLUS DC and Switching Characteristics
PLL Behavior at Brownout Condition
Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout activation levels (see Figure 2-1 and Figure 2-2 on page 2-5 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V 0.25 V for V5 devices, and 0.75 V 0.2 V for V2 devices), the PLL output lock signal goes Low and/or the output clock is lost. Refer to the "Brownout Voltage" section in the "Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the IGLOO PLUS Device Family User's Guide for information on clock and lock recovery.
Internal Power-Up Activation Sequence
1. Core 2. Input buffers 3. Output buffers, after 200 ns delay from input buffer activation To make sure the transition from input buffers to output buffers is clean, ensure that there is no path longer than 100 ns from input buffer to output buffer in your design.
VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V
Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL, VOH / VOL, etc.
Region 1: I/O Buffers are OFF
VCC = 1.425 V
Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI / VCC are below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification.
Activation trip point: Va = 0.85 V 0.25 V Deactivation trip point: Vd = 0.75 V 0.25 V
Region 1: I/O buffers are OFF
Activation trip point: Va = 0.9 V 0.3 V Deactivation trip point: Vd = 0.8 V 0.3 V
Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V
VCCI
Figure 2-1 *
V5 Devices - I/O State as a Function of VCCI and VCC Voltage Levels
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IGLOO PLUS Low Power Flash FPGAs
VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V
Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL , VOH / VOL , etc.
Region 1: I/O Buffers are OFF
VCC = 1.14 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Activation trip point: Va = 0.85 V 0.2 V Deactivation trip point: Vd = 0.75 V 0.2 V Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification.
Region 1: I/O buffers are OFF
Activation trip point: Va = 0.9 V 0.15 V Deactivation trip point: Vd = 0.8 V 0.15 V
Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.14 V,1.425 V, 1.7 V, 2.3 V, or 3.0 V
VCCI
Figure 2-2 *
V2 Devices - I/O State as a Function of VCCI and VCC Voltage Levels
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IGLOO PLUS DC and Switching Characteristics
Thermal Characteristics
Introduction
The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction temperature to be higher than the ambient temperature. EQ 1 can be used to calculate junction temperature. TJ = Junction Temperature = T + TA EQ 1 where: TA = Ambient temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P ja = Junction-to-ambient of the package. ja numbers are located in Figure 2-5. P = Power dissipation
Package Thermal Characteristics
The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for ja are shown for two air flow rates. The maximum operating junction temperature is 100C. EQ 2 shows a sample calculation of the maximum operating power dissipation allowed for a 484-pin FBGA package at commercial temperature and in still air. Max. junction temp. (C) - Max. ambient temp. (C) 100C - 70C Maximum Power Allowed = ----------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 1.46 W ja (C/W) 20.5C/W EQ 2 Table 2-5 * Package Thermal Resistivities ja Package Type Chip Scale Package (CSP) Pin Count 201 281 289 Very Thin Quad Flat Package (VQFP) 128 176 jc TBD TBD TBD TBD TBD Still Air TBD TBD TBD TBD TBD 200 ft./ min. TBD TBD TBD TBD TBD 500 ft./ min. TBD TBD TBD TBD TBD Units C/W C/W C/W C/W C/W
Temperature and Voltage Derating Factors
Table 2-6 * Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70C, VCC = 1.425 V) For IGLOO PLUS V2 or V5 devices, 1.5 V DC Core Supply Voltage Array Voltage VCC (V) 1.425 1.5 1.575 Junction Temperature (C) -40C 0.934 0.855 0.799 0C 0.953 0.874 0.816 25C 0.971 0.891 0.832 70C 1.000 0.917 0.857 85C 1.007 0.924 0.864 100C 1.013 0.929 0.868
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IGLOO PLUS Low Power Flash FPGAs Table 2-7 * Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70C, VCC = 1.14 V) For IGLOO PLUS V2, 1.2 V DC Core Supply Voltage Array Voltage VCC (V) 1.14 1.2 1.26 Junction Temperature (C) -40C 0.963 0.853 0.781 0C 0.975 0.865 0.792 25C 0.989 .0877 0.803 70C 1.000 0.893 0.813 85C 1.007 0.893 0.819 100C 1.011 0.897 0.822
Calculating Power Dissipation
Quiescent Supply Current
Quiescent supply current (IDD) calculation depends on multiple factors, including operating voltages (VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power mode usage. Actel recommends using the Power Calculator and SmartPower software estimation tools to evaluate the projected static and active power based on the user design, power mode usage, operating voltage, and temperature. Table 2-8 * Power Supply State per Mode Power Supply Configurations Modes/Power Supplies Flash*Freeze Sleep Shutdown No Flash*Freeze VCC On Off Off On VCCPLL On Off Off On VCCI On On Off On VJTAG On Off Off On VPUMP On/off/floating Off Off On/off/floating
Note: Off: Power Supply level = 0 V Table 2-9 * Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Flash*Freeze Mode* Core Voltage Typical (25C) 1.2 V 1.5 V AGLP030 4 6 AGLP060 8 10 AGLP125 13 18 Units A A
* IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents. Table 2-10 * Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Sleep Mode* ICCI Current VCCI = 1.2 V (per bank) Typical (25C) VCCI = 1.5 V (per bank) Typical (25C) VCCI = 1.8 V (per bank) Typical (25C) VCCI = 2.5 V (per bank) Typical (25C) VCCI = 3.3 V (per bank) Typical (25C) Note: *IDD = NBANKS * ICCI Core Voltage 1.2 V 1.2 V / 1.5 V 1.2 V / 1.5 V 1.2 V / 1.5 V 1.2 V / 1.5 V AGLP030 AGLP060 AGLP125 1.7 1.8 1.9 2.2 2.5 1.7 1.8 1.9 2.2 2.5 1.7 1.8 1.9 2.2 2.5 Units A A A A A
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IGLOO PLUS DC and Switching Characteristics Table 2-11 * Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Shutdown Mode Core Voltage Typical (25C) 1.2 V / 1.5 V AGLP030 0 AGLP060 0 AGLP125 0 Units A
Table 2-12 * Quiescent Supply Current (IDD), No IGLOO PLUS Flash*Freeze Mode 1 Core Voltage ICCA Current 2 1.2 V 1.5 V ICCI or IJTAG Current VCCI / VJTAG = 1.2 V (per bank) Typical (25C) VCCI / VJTAG = 1.5 V (per bank) Typical (25C) VCCI / VJTAG = 1.8 V (per bank) Typical (25C) VCCI / VJTAG = 2.5 V (per bank) Typical (25C) VCCI / VJTAG = 3.3 V (per bank) Typical (25C) Notes:
1. IDD = NBANKS * ICCI + ICCA. JTAG counts as one bank when powered. 2. Includes VCC, VCCPLL, and VPUMP currents.
AGLP030
AGLP060 AGLP125
Units
Typical (25C)
6 16
10 20
13 28
A A
1.2 V 1.2 V / 1.5 V 1.2 V / 1.5 V 1.2 V / 1.5 V 1.2 V / 1.5 V
1.7 1.8 1.9 2.2 2.5
1.7 1.8 1.9 2.2 2.5
1.7 1.8 1.9 2.2 2.5
A A A A A
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IGLOO PLUS Low Power Flash FPGAs
Power per I/O Pin
Table 2-13 * Summary of I/O Input Buffer Power (per pin) - Default I/O Software Settings VCCI (V) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVTTL / 3.3 V LVCMOS - Schmitt Trigger 3.3 V LVCMOS Wide Range
2
Dynamic Power PAC9 (W/MHz) 1
3.3 3.3 3.3 3.3 2.5 2.5 1.8 1.8 1.5 1.5 1.2 1.2 1.2 1.2
16.26 18.95 16.26 18.95 4.59 6.01 1.61 1.70 0.96 0.90 0.55 0.47 0.55 0.47
3.3 V LVCMOS Wide Range2 - Schmitt Trigger 2.5 V LVCMOS 2.5 V LVCMOS - Schmitt Trigger 1.8 V LVCMOS 1.8 V LVCMOS - Schmitt Trigger 1.5 V LVCMOS (JESD8-11) 1.5 V LVCMOS (JESD8-11) - Schmitt Trigger 1.2 V LVCMOS
3
1.2 V LVCMOS3 - Schmitt Trigger 1.2 V LVCMOS Wide Range3
3
1.2 V LVCMOS Wide Range - Schmitt Trigger Notes:
1. PAC9 is the total dynamic power measured on VCCI. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 3. Applicable for IGLOO PLUS V2 devices only, operating at VCCI VCC.
Table 2-14 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings1 CLOAD (pF) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range3 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 1.2 V LVCMOS4 1.2 V LVCMOS Wide Range Notes:
1. 2. 3. 4. Dynamic power consumption is given for standard load and software default drive strength and output slew. PAC10 is the total dynamic power measured on VCCI. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. Applicable for IGLOO PLUS V2 devices only, operating at VCCI VCC.
4
VCCI (V)
Dynamic Power PAC10 (W/MHz)2
5 5 5 5 5 5 5
3.3 3.3 2.5 1.8 1.5 1.2 1.2
127.11 127.11 70.71 35.57 24.30 15.22 15.22
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IGLOO PLUS DC and Switching Characteristics
Power Consumption of Various Internal Resources
Table 2-15 * Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices For IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage Device Specific Dynamic Power (W/MHz) Parameter PAC1 PAC2 PAC3 PAC4 PAC5 PAC6 PAC7 PAC8 PAC9 PAC10 PAC11 PAC12 PAC13 Definition Clock contribution of a Global Rib Clock contribution of a Global Spine Clock contribution of a VersaTile row Clock contribution of a VersaTile used as a sequential module First contribution of a VersaTile used as a sequential module Second contribution of a VersaTile used as a sequential module Contribution of a VersaTile used as a combinatorial module Average contribution of a routing net Contribution of an I/O input pin (standard-dependent) Contribution of an I/O output pin (standard-dependent) Average contribution of a RAM block during a read operation Average contribution of a RAM block during a write operation Dynamic contribution for PLL AGLP125 AGLP060 AGLP030 11.03 0.81 9.3 0.81 0.81 0.11 0.057 0.207 0.17 0.7 See Table 2-13 on page 2-9. See Table 2-14 on page 2-9. 25.00 30.00 2.70 9.3 0.41
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IGLOO PLUS Low Power Flash FPGAs Table 2-16 * Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices For IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage Device-Specific Static Power (mW) Parameter PDC1 PDC2 PDC3 PDC4 PDC5 Notes:
1. This is the minimum contribution of the PLL when operating at lowest frequency. 2. For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or the SmartPower tool in Actel Libero(R) Integrated Design Environment (IDE) software.
Definition Array static power in Active mode Array static power in Static (Idle) mode Array static power in Flash*Freeze mode Static PLL contribution Bank quiescent power (VCCI-dependent)
AGLP125
AGLP060
AGLP030
See Table 2-12 on page 2-8 See Table 2-11 on page 2-8 See Table 2-9 on page 2-7 1.841 See Table 2-12 on page 2-8
Table 2-17 * Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices For IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage Device-Specific Dynamic Power (W/MHz) Parameter PAC1 PAC2 PAC3 PAC4 PAC5 PAC6 PAC7 PAC8 PAC9 PAC10 PAC11 PAC12 PAC13 Definition Clock contribution of a Global Rib Clock contribution of a Global Spine Clock contribution of a VersaTile row Clock contribution of a VersaTile used as a sequential module First contribution of a VersaTile used as a sequential module Second contribution of a VersaTile used as a sequential module Contribution of a VersaTile used as a combinatorial module Average contribution of a routing net Contribution of an I/O input pin (standard-dependent) Contribution of an I/O output pin (standard-dependent) Average contribution of a RAM block during a read operation Average contribution of a RAM block during a write operation Dynamic contribution for PLL AGLP125 AGLP060 AGLP030 7.07 0.52 5.96 0.52 0.52 0.07 0.045 0.186 0.11 0.45 See Table 2-13 on page 2-9 See Table 2-14 on page 2-9 25.00 30.00 2.10 5.96 0.26
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IGLOO PLUS DC and Switching Characteristics Table 2-18 * Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices For IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage Device-Specific Static Power (mW) Parameter PDC1 PDC2 PDC3 PDC4 PDC5 Notes:
1. This is the minimum contribution of the PLL when operating at lowest frequency. 2. For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or the SmartPower tool in Actel Libero IDE software.
Definition Array static power in Active mode Array static power in Static (Idle) mode Array static power in Flash*Freeze mode Static PLL contribution Bank quiescent power (VCCI-dependent)
AGLP125
AGLP060
AGLP030
See Table 2-12 on page 2-8 See Table 2-11 on page 2-8 See Table 2-9 on page 2-7 0.901 See Table 2-12 on page 2-8
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software. The power calculation methodology described below uses the following variables: * * * * * * * * The number of PLLs as well as the number and the frequency of each output clock generated The number of combinatorial and sequential cells used in the design The internal clock frequencies The number and the standard of I/O pins used in the design The number of RAM blocks used in the design Toggle rates of I/O pins as well as VersaTiles--guidelines are provided in Table 2-19 on page 2-14. Enable rates of output buffers--guidelines are provided for typical applications in Table 2-20 on page 2-14. Read rate and write rate to the memory--guidelines are provided for typical applications in Table 2-20 on page 2-14. The calculation should be repeated for each clock domain defined in the design.
Methodology
Total Power Consumption--PTOTAL
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption. PDYN is the total dynamic power consumption.
Total Static Power Consumption--PSTAT
PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5
NBANKS is the number of I/O banks powered in the design.
Total Dynamic Power Consumption--PDYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution--PCLOCK
PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK
NSPINE is the number of global spines used in the user design--guidelines are provided in Table 2-19 on page 2-14. NROW is the number of VersaTile rows used in the design--guidelines are provided in Table 2-19 on page 2-14.
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IGLOO PLUS Low Power Flash FPGAs
FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution--PS-CELL
PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1.
1
is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-19 on page 2-14. FCLK is the global clock signal frequency.
Combinatorial Cells Contribution--PC-CELL
PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1
is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-19 on page 2-14. FCLK is the global clock signal frequency.
Routing Net Contribution--PNET
PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
1
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
is the toggle rate of VersaTile outputs--guidelines are provided in Table 2-19 on page 2-14. FCLK is the global clock signal frequency.
I/O Input Buffer Contribution--PINPUTS
PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design. FCLK is the global clock signal frequency.
2 is the I/O buffer toggle rate--guidelines are provided in Table 2-19 on page 2-14.
I/O Output Buffer Contribution--POUTPUTS
POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
2 is the I/O buffer toggle rate--guidelines are provided in Table 2-19 on page 2-14. 1 is the I/O buffer enable rate--guidelines are provided in Table 2-20 on page 2-14.
FCLK is the global clock signal frequency.
RAM Contribution--PMEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3
NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency.
2 is the RAM enable rate for read operations.
3 is the RAM enable rate for write operations--guidelines are provided in Table 2-20 on page 2-14.
PLL Contribution--PPLL
PPLL = PDC4 + PAC13 *FCLKOUT
FWRITE-CLOCK is the memory write clock frequency.
FCLKOUT is the output clock frequency.1
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IGLOO PLUS DC and Switching Characteristics
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: * * The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. The average toggle rate of an 8-bit counter is 25%: - - - - - - Bit 0 (LSB) = 100% Bit 1 Bit 2 ... Bit 7 (MSB) = 0.78125% Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 = 50% = 25%
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-19 * Toggle Rate Guidelines Recommended for Power Calculation Component Definition Toggle rate of VersaTile outputs I/O buffer toggle rate Guideline 10% 10%
1 2
Component
Table 2-20 * Enable Rate Guidelines Recommended for Power Calculation Definition I/O output buffer enable rate RAM enable rate for read operations RAM enable rate for write operations Guideline 100% 12.5% 12.5%
1 2 3
1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution.
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IGLOO PLUS Low Power Flash FPGAs
User I/O Characteristics
Timing Model
I/O Module (Non-Registered) Combinational Cell Y tPD = 1.40 ns Combinational Cell Y tPD = 0.89 ns tDP = 1.62 ns Combinational Cell Y tPD = 1.98 ns Combinational Cell I/O Module (Registered) tPY = 1.06 ns tDP = 1.70 ns Input LVCMOS 2.5 V D Q tPD = 1.24 ns Combinational Cell Y tICLKQ = 0.63 ns tISUD = 0.18 ns Input LVTTL Clock Register Cell tPY = 0.85 ns I/O Module (Non-Registered) tCLKQ = 0.80 ns tSUD = 0.84 ns tPY = 1.15 ns Input LVTTL Clock tPY = 0.85 ns D Q Combinational Cell Y tPD = 0.87 ns tCLKQ = 0.80 ns tSUD = 0.84 ns Input LVTTL Clock tPY = 0.85 ns Register Cell D Q D tPD = 0.86 ns tDP = 2.07 ns I/O Module (Non-Registered) LVCMOS 1.5 V Output drive strength = 4 mA High slew rate Y LVTTL Output drive strength = 8 mA High slew rate tDP = 1.62 ns I/O Module (Non-Registered) I/O Module (Non-Registered) LVTTL Output drive strength = 12 mA High slew rate LVCMOS 2.5 V Output Drive Strength = 12 mA High Slew Rate
I/O Module (Registered) Q tDP = 1.62 ns tOCLKQ = 0.89 ns tOSUD = 0.18 ns LVTTL 3.3 V Output drive strength = 12 mA High slew rate
LVCMOS 1.5 V
Figure 2-3 *
Timing Model Operating Conditions: STD Speed, Commercial Temperature Range (TJ = 70C), Worst-Case VCC = 1.425 V, for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices
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IGLOO PLUS DC and Switching Characteristics
tPY
tDIN
PAD
D Y
Q DIN To Array
CLK
tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F))
I/O Interface
VIH
PAD
Vtrip
Vtrip VCC
VIL
50% Y GND tPY (R) tPY (F) VCC 50% DIN GND tDOUT (R)
Figure 2-4 *
50%
50% tDOUT (F)
Input Buffer Timing Model and Delays (example)
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IGLOO PLUS Low Power Flash FPGAs
tDOUT DQ DOUT D From Array I/O Interface CLK
tDP PAD Std Load tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F)) tDOUT VCC 50% VCC 50% 50% VOH Vtrip Vtrip VOL tDP (R) tDP (F) (F)
tDOUT (R) 50%
D
0V
DOUT
0V
PAD
Figure 2-5 *
Output Buffer Model and Delays (example)
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IGLOO PLUS DC and Switching Characteristics
tEOUT D E Q tZL, tZH, tHZ, tLZ, tZLS, tZHS
CLK
EOUT D D Q DOUT CLK PAD
I/O Interface
tEOUT = MAX(tEOUT(r), tEOUT(f)) VCC
D VCC E 50% tEOUT (R) 50% EOUT tZL PAD Vtrip VOL 50% tEOUT (F) VCC 50% tHZ 90% VCCI Vtrip 10% VCCI 50% tZH VCCI 50% tLZ
VCC D VCC E 50% tEOUT (R) 50% tZLS PAD Vtrip VOL Vtrip 50% VCC EOUT 50% VOH 50% tZHS tEOUT (F)
Figure 2-6 *
Tristate Output Buffer Timing Model and Delays (example)
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IGLOO PLUS Low Power Flash FPGAs
Overview of I/O Performance
Summary of I/O DC Input and Output Levels - Default I/O Software Settings
Table 2-21 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings Equiv. Software Default Drive Drive Strength Slew Min. Strength Option2 Rate V 12 mA High -0.3 12 mA High -0.3 12 mA High -0.3 8 mA 4 mA 2 mA 2 mA VIL VIH VOL VOH IOL1 IOH1
I/O Standard
Max. V 0.8 0.8 0.7
Min. V 2 2 1.7
Max. V 3.6 3.6 3.6 3.6 3.6 3.6 3.6
Max. V 0.4 0.2 0.7 0.45
Min. V 2.4
mA mA 12 12
3.3 V LVTTL / 12 mA 3.3 V LVCMOS 3.3 V LVCMOS 100 A Wide Range3 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS4 12 mA 8 mA 4 mA 2 mA
VDD 3 0.2 0.1 0.1 1.7 VCCI - 0.45 12 8 4 2 12 8 4 2
High -0.3 0.35 * VCCI 0.65 * VCCI High -0.3 0.35 * VCCI 0.65 * VCCI High -0.3 0.35 * VCCI 0.65 * VCCI High -0.3 0.3 * VCCI 0.7 * VCCI
0.25 * VCCI 0.75 * VCCI 0.25 * VCCI 0.75 * VCCI 0.1
1.2 V LVCMOS 100 A Wide Range4,5 Notes:
VCCI - 0.1 0.1 0.1
1. Currents are measured at 85C junction temperature. 2. Note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range are applicable to 100 A drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 4. Applicable to IGLOO PLUS V2 devices operating at VCCI VCC. 5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.
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IGLOO PLUS DC and Switching Characteristics Table 2-22 * Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions Commercial1 IIL3 DC I/O Standards 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS
5 5
Industrial2 IIH4 A 10 10 10 10 10 10 10 IIL3 A 15 15 15 15 15 15 15 IIH4 A 15 15 15 15 15 15 15
A 10 10 10 10 10 10 10
1.2 V LVCMOS Wide Range Notes:
1. 2. 3. 4.
Commercial range (0C < TA < 70C) Industrial range (-40C < TA < 85C) IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 5. Applicable to IGLOO PLUS V2 devices operating at VCCI VCC.
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IGLOO PLUS Low Power Flash FPGAs
Summary of I/O Timing Characteristics - Default I/O Software Settings
Table 2-23 * Summary of AC Measuring Points Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range Table 2-24 * I/O AC Parameter Definitions Parameter tDP tPY tDOUT tEOUT tDIN tHZ tZH tLZ tZL tZHS tZLS Parameter Definition Data to Pad delay through the Output Buffer Pad to Data delay through the Input Buffer Data to Output Buffer delay through the I/O interface Enable to Output Buffer Tristate Control delay through the I/O interface Input Buffer to Data delay through the I/O interface Enable to Pad delay through the Output Buffer--High to Z Enable to Pad delay through the Output Buffer--Z to High Enable to Pad delay through the Output Buffer--Low to Z Enable to Pad delay through the Output Buffer--Z to Low Enable to Pad delay through the Output Buffer with delayed enable--Z to High Enable to Pad delay through the Output Buffer with delayed enable--Z to Low Measuring Trip Point (Vtrip) 1.4 V 1.4 V 1.2 V 0.90 V 0.75 V 0.60 V 0.60 V
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IGLOO PLUS DC and Switching Characteristics Table 2-25 * Summary of I/O Timing Characteristics--Software Default Settings, STD Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Equivalent Software Default Drive Strength Option1
External Resistor ()
Capacitive Load (pF)
Drive Strength
I/O Standard
Slew Rate
tE O U T
tDOUT
tPY
3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range2 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Notes:
12 mA 12 mA High 5 pF
-
0.97 0.97 0.97 0.97 0.97
1.76 0.18 0.85 1.15 0.66 1.80 1.39 2.20 2.64 2.47 0.18 1.18 1.64 0.66 2.48 1.91 3.16 3.76 1.77 0.18 1.06 1.22 0.66 1.81 1.51 2.22 2.56 2.00 0.18 1.00 1.43 0.66 2.04 1.76 2.29 2.55 2.29 0.18 1.16 1.62 0.66 2.33 2.00 2.37 2.57
tHZ
ns ns ns ns ns
100 A 12 mA High 5 pF - 12 mA 12 mA High 5 pF 8 mA 8 mA 4 mA 4 mA High 5 pF High 5 pF - - -
1. Note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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Units
tPYS
tDIN
tDP
tZH
tZL
tLZ
IGLOO PLUS Low Power Flash FPGAs Table 2-26 * Summary of I/O Timing Characteristics--Software Default Settings, STD Speed Grade Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Equivalent Software Default Drive Strength Option1
External Resistor ()
Capacitive Load (pF)
Drive Strength
I/O Standard
Slew Rate
tE O U T
tDOUT
tPY)
tDIN
tZH
3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range2 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range3 Notes:
12 mA 12 mA High 5 pF 100 A 12 mA High 5 pF 12 mA 12 mA High 5 pF 8 mA 8 mA High 5 pF 4 mA 4 mA High 5 pF 2 mA 2 mA High 5 pF 100 A 2 mA High 5 pF
- 0.98 2.31 0.19 0.99 1.37 0.67 2.34 1.86 2.65 3.38 ns - 0.98 3.21 0.19 1.32 1.92 0.67 3.21 2.52 3.73 4.73 ns - 0.98 2.29 0.19 1.19 1.40 0.67 2.32 1.94 2.65 3.27 ns - 0.98 2.45 0.19 1.12 1.61 0.67 2.48 2.16 2.71 3.16 ns - 0.98 2.71 0.19 1.26 1.80 0.67 2.75 2.39 2.78 3.15 ns - 0.98 3.38 0.19 1.57 2.34 0.67 3.26 2.78 2.99 3.24 ns - 0.98 3.38 0.19 1.57 2.34 0.67 3.26 2.78 2.99 3.24 ns
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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tHZ
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Units
tPYS
tDP
tZL
tLZ
IGLOO PLUS DC and Switching Characteristics
Detailed I/O DC Characteristics
Table 2-27 * Input Capacitance Symbol CIN CINCLK Input capacitance Input capacitance on the clock pin Definition Conditions VIN = 0, f = 1.0 MHz VIN = 0, f = 1.0 MHz Min. Max. 8 8 Units pF pF
Table 2-28 * I/O Output Buffer Maximum Resistances 1 Standard 3.3 V LVTTL / 3.3V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 100 A 2 mA 4 mA 6 mA 8 mA 12 mA 1.8 V LVCMOS 2 mA 4 mA 6 mA 8 mA 1.5 V LVCMOS 2 mA 4 mA 1.2 V LVCMOS 1.2 V LVCMOS Wide Range Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS model on the Actel website at http://www.actel.com/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax - VOHspec) / IOHspec 4. Applicable to IGLOO PLUS V2 devices operating at VCCI VCC.
4
RPULL-DOWN () 2 100 100 50 50 25 25
RPULL-UP () 3 300 300 150 150 75 75
Same as equivalent software default drive 100 100 50 50 25 200 100 50 50 200 100 157.5 157.5 200 200 100 100 50 225 112 56 56 224 112 163.8 163.8
2 mA 100 A
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IGLOO PLUS Low Power Flash FPGAs Table 2-29 * I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R(WEAK PULL-UP)1 () VCCI 3.3 V 3.3 V (wide range I/Os) 2.5 V 1.8 V 1.5 V 1.2 V 1.2 V (wide range I/Os) Notes:
1. R(WEAK PULL-UP-MAX) = (VCCImax - VOHspec) / I(WEAK PULL-UP-MIN) 2. R(WEAK PULLDOWN-MAX) = (VOLspec) / I(WEAK PULLDOWN-MIN)
R(WEAK PULL-DOWN)2 () Min. 10 K 10 K 12 K 17 K 19 K 25 K 19 K Max. 45 K 45 K 74 K 110 K 140 K 150 K 150 K
Min. 10 K 10 K 11 K 18 K 19 K 25 K 19 K
Max. 45 K 45 K 55 K 70 K 90 K 110 K 110 K
Table 2-30 * I/O Short Currents IOSH/IOSL Drive Strength 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 100 A 2 mA 4 mA 6 mA 8 mA 12 mA 1.8 V LVCMOS 2 mA 4 mA 6 mA 8 mA 1.5 V LVCMOS 2 mA 4 mA 1.2 V LVCMOS 1.2 V LVCMOS Wide Range * TJ = 100C 2 mA 100 A IOSL (mA)* 27 27 54 54 109 109 IOSH (mA)* 25 25 51 51 103 103
Same as equivalent software default drive 18 18 37 37 74 11 22 44 44 16 33 26 26 16 16 32 32 65 9 17 35 35 13 25 20 20
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IGLOO PLUS DC and Switching Characteristics The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis. For example, at 100C, the short current condition would have to be sustained for more than six months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-31 * Duration of Short Circuit Event before Failure Temperature -40C 0C 25C 70C 85C 100C Time before Failure > 20 years > 20 years > 20 years 5 years 2 years 6 months
Table 2-32 * Schmitt Trigger Input Hysteresis Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers Input Buffer Configuration 3.3 V LVTTL/LVCMOS (Schmitt trigger mode) 2.5 V LVCMOS (Schmitt trigger mode) 1.8 V LVCMOS (Schmitt trigger mode) 1.5 V LVCMOS (Schmitt trigger mode) 1.2 V LVCMOS (Schmitt trigger mode) Table 2-33 * I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer LVTTL/LVCMOS (Schmitt trigger disabled) LVTTL/LVCMOS (Schmitt trigger enabled) Input Rise/Fall Time (min.) No requirement No requirement Input Rise/Fall Time (max.) 10 ns * No requirement, but input noise voltage cannot exceed Schmitt hysteresis. Reliability 20 years (100C) 20 years (100C) Hysteresis Value (typ.) 240 mV 140 mV 80 mV 60 mV 40 mV
* The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.
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IGLOO PLUS Low Power Flash FPGAs
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor-Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-34 * Minimum and Maximum DC Input and Output Levels 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. 5. Software default selection highlighted in gray.
VIL Min. V -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max. V 0.8 0.8 0.8 0.8 0.8 0.8 Min. V 2 2 2 2 2 2
VIH Max. V 3.6 3.6 3.6 3.6 3.6 3.6
VOL Max. V 0.4 0.4 0.4 0.4 0.4 0.4
VOH Min. V 2.4 2.4 2.4 2.4 2.4 2.4
IOL IOH mA mA 2 4 6 8 12 16 2 4 6 8 12 16
IOSL Max. mA3 25 25 51 51 103 103
IOSH Max. mA3 27 27 54 54 109 109
IIL1 IIH2 A4 A4 10 10 10 10 10 10 10 10 10 10 10 10
Test Point Datapath 5 pF
R=1k Test Point Enable Path
R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ
Figure 2-7 *
AC Loading
Table 2-35 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) 3.3 Measuring Point* (V) 1.4 CLOAD (pF) 5
* Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.
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IGLOO PLUS DC and Switching Characteristics
Timing Characteristics
Applies to 1.5 V DC Core Voltage Table 2-36 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade STD STD STD STD STD tDOUT 0.97 0.97 0.97 0.97 0.97 tDP 3.94 3.20 3.20 2.72 2.72 tDIN 0.18 0.18 0.18 0.18 0.18 tPY 0.85 0.85 0.85 0.85 0.85 tPYS 1.15 1.15 1.15 1.15 1.15 tEOUT 0.66 0.66 0.66 0.66 0.66 tZL 4.02 3.27 3.27 2.78 2.78 tZH 3.46 2.94 2.94 2.57 2.57 tLZ 1.82 2.04 2.04 2.20 2.20 tHZ 1.87 2.27 2.27 2.53 2.53 Units ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-37 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray.
Speed Grade STD STD STD STD STD
tDOUT 0.97 0.97 0.97 0.97 0.97
tDP 2.36 1.96 1.96 1.76 1.76
tDIN 0.18 0.18 0.18 0.18 0.18
tPY 0.85 0.85 0.85 0.85 0.85
tPYS 1.15 1.15 1.15 1.15 1.15
tEOUT 0.66 0.66 0.66 0.66 0.66
tZL 2.41 2.01 2.01 1.80 1.80
tZH 1.90 1.56 1.56 1.39 1.39
tLZ 1.82 2.04 2.04 2.20 2.20
tHZ 1.98 2.38 2.38 2.64 2.64
Units ns ns ns ns ns
Applies to 1.2 V DC Core Voltage Table 2-38 * 3.3 V LVTTL / 3.3 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade STD STD STD STD STD tDOUT 0.98 0.98 0.98 0.98 0.98 tDP 4.56 3.80 3.80 3.31 3.31 tDIN 0.19 0.19 0.19 0.19 0.19 tPY 0.99 0.99 0.99 0.99 0.99 tPYS 1.37 1.37 137 1.37 1.37 tEOUT 0.67 0.67 0.67 0.67 0.67 tZL 4.63 3.96 3.86 3.36 3.36 tZH 3.98 3.45 3.45 3.07 3.07 tLZ 2.26 2.49 2.49 2.65 2.65 tHZ 2.57 2.98 2.98 3.25 3.25 Units ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-39 * 3.3 V LVTTL / 3.3 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray
Speed Grade STD STD STD STD STD
tDOUT 0.98 0.98 0.98 0.98 0.98
tDP 2.92 2.52 2.52 2.31 2.31
tDIN 0.19 0.19 0.19 0.19 0.19
tPY 0.99 0.99 0.99 0.99 0.99
tPYS 1.37 1.37 1.37 1.37 1.37
tEOUT 0.67 0.67 0.67 0.67 0.67
tZL 2.97 2.56 2.56 2.34 2.34
tZH 2.38 2.03 2.03 1.86 1.86
tLZ 2.25 2.49 2.49 2.65 2.65
tHZ 2.70 3.11 3.11 3.38 3.38
Units ns ns ns ns ns
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IGLOO PLUS Low Power Flash FPGAs
3.3 V LVCMOS Wide Range
Table 2-40 * Minimum and Maximum DC Input and Output Levels Equivalent Software Default Drive 3.3 V LVCMOS Strength Wide Range Option1 Drive Strength 100 A 100 A 100 A 100 A 100 A 100 A Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < V CCI. Input current is larger when operating outside recommended ranges. 4. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 5. Currents are measured at 85C junction temperature. 6. Software default selection highlighted in gray.
VIL Min. V Max. V 0.8 0.8 0.8 0.8 0.8 0.8
VIH Min. Max. V V 2 2 2 2 2 2 3.6 3.6 3.6 3.6 3.6 3.6
VOL Max. V 0.2 0.4 0.4 0.4 0.4 0.4
VOH Min. V
IOL A
IOH A
IOSL Max. A4 25 25 51 51 103 103
IOSH Max. A4 27 27 54 54 109 109
IIL2
IIH3
A5 A5 10 10 10 10 10 10 10 10 10 10 10 10
2 mA 4 mA 6 mA 8 mA 12 mA 16 mA
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3
VDD - 0.2 100 100 VDD - 0.2 100 100 VDD - 0.2 100 100 VDD - 0.2 100 100 VDD - 0.2 100 100 VDD - 0.2 100 100
Table 2-41 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) 3.3 Measuring Point* (V) 1.4 CLOAD (pF) 5
* Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.
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IGLOO PLUS DC and Switching Characteristics
Timing Characteristics
Applies to 1.5 V DC Core Voltage Table 2-42 * 3.3 V LVCMOS Wide Range Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Equivalent Software Default Drive Drive Strength Strength Option1 100 A 100 A 100 A 100 A 100 A Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Speed Grade STD STD STD STD STD
tDOUT 0.97 0.97 0.97 0.97 0.97
tDP 5.85 4.70 4.70 3.96 3.96
tDIN 0.18 0.18 0.18 0.18 0.18
tPY 1.18 1.18 1.18 1.18 1.18
tPYS 1.64 1.64 1.64 1.64 1.64
tEOUT 0.66 0.66 0.66 0.66 0.66
tZL 5.86 4.72 4.72 3.98 3.98
tZH 5.05 4.27 4.27 3.70 3.70
tLZ 2.57 2.92 2.92 3.16 3.16
tHZ 2.57 3.19 3.19 3.59 3.59
Units ns ns ns ns ns
4 mA 6 mA 8 mA 12 mA 16 mA
Table 2-43 * 3.3 V LVCMOS Wide Range High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Equivalent Software Default Drive Drive Strength Strength Option1 100 A 100 A 100 A 100 A 100 A Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 3. Software default selection highlighted in gray.
Speed Grade STD STD STD STD STD
tDOUT 0.97 0.97 0.97 0.97 0.97
tDP 3.39 2.79 2.79 2.47 2.47
tDIN 0.18 0.18 0.18 0.18 0.18
tPY 1.18 1.18 1.18 1.18 1.18
tPYS 1.64 1.64 1.64 1.64 1.64
tEOUT 0.66 0.66 0.66 0.66 0.66
tZL 3.41 2.80 2.80 2.48 2.48
tZH 2.69 2.17 2.17 1.91 1.91
tLZ 2.57 2.92 2.92 3.16 3.16
tHZ 2.73 3.36 3.36 3.76 3.76
Units ns ns ns ns ns
4 mA 6 mA 8 mA 12 mA 16 mA
Applies to 1.2 V DC Core Voltage
2- 30
R ev i sio n 1 1
IGLOO PLUS Low Power Flash FPGAs Table 2-44 * 3.3 V LVCMOS Wide Range Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Equivalent Software Default Drive Drive Strength Strength Option1 100 A 100 A 100 A 100 A 100 A Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Speed Grade STD STD STD STD STD
tDOUT 0.98 0.98 0.98 0.98 0.98
tDP 6.68 5.51 5.51 4.75 4.75
tDIN 0.19 0.19 0.19 0.19 0.19
tPY 1.32 1.32 1.32 1.32 1.32
tPYS 1.92 1.92 1.92 1.92 1.92
tEOUT 0.67 0.67 0.67 0.67 0.67
tZL 6.68 5.51 5.51 4.75 4.75
tZH 5.74 4.94 4.94 4.36 4.36
tLZ 3.13 3.48 3.48 3.73 3.73
tHZ 3.47 4.11 4.11 4.52 4.52
Units ns ns ns ns ns
4 mA 6 mA 8 mA 12 mA 16 mA
Table 2-45 * 3.3 V LVCMOS Wide Range High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Equivalent Software Default Drive Drive Strength Strength Option1 100 A 100 A 100 A 100 A 100 A Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 3. Software default selection highlighted in gray.
Speed Grade STD STD STD STD STD
tDOUT 0.98 0.98 0.98 0.98 0.98
tDP 4.16 3.54 3.54 3.21 3.21
tDIN 0.19 0.19 0.19 0.19 0.19
tPY 1.32 1.32 1.32 1.32 1.32
tPYS 1.92 1.92 1.92 1.92 1.92
tEOUT 0.67 0.67 0.67 0.67 0.67
tZL 4.16 3.54 3.54 3.21 3.21
tZH 3.32 2.79 2.79 2.52 2.52
tLZ 3.12 3.48 3.48 3.73 3.73
tHZ 3.66 4.31 4.31 4.73 4.73
Units ns ns ns ns ns
4 mA 6 mA 8 mA 12 mA 16 mA
R ev i si o n 1 1
2- 31
IGLOO PLUS DC and Switching Characteristics
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 2.5 V applications. Table 2-46 * Minimum and Maximum DC Input and Output Levels 2.5 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. 5. Software default selection highlighted in gray.
VIL Min. V -0.3 -0.3 -0.3 -0.3 -0.3 Max. V 0.7 0.7 0.7 0.7 0.7 Min. V 1.7 1.7 1.7 1.7 1.7
VIH Max. V 3.6 3.6 3.6 3.6 3.6
VOL Max. V 0.7 0.7 0.7 0.7 0.7
VOH Min. V 1.7 1.7 1.7 1.7 1.7
IOL
IOH
IOSL Max. mA3 16 16 32 32 65
IOSH Max. mA3 18 18 37 37 74
IIL1
IIH2
mA mA 2 4 6 8 12 2 4 6 8 12
A4 A4 10 10 10 10 10 10 10 10 10 10
Test Point Datapath 5 pF
R=1k Test Point Enable Path
R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ
Figure 2-8 *
AC Loading
Table 2-47 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) 2.5 Measuring Point* (V) 1.2 CLOAD (pF) 5
* Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.
2- 32
R ev i sio n 1 1
IGLOO PLUS Low Power Flash FPGAs
Timing Characteristics
Applies to 1.5 V DC Core Voltage Table 2-48 * 2.5 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Drive Strength 4 mA 6 mA 8 mA 12 mA Speed Grade STD STD STD STD tDOUT 0.97 0.97 0.97 0.97 tDP 4.44 3.61 3.61 3.07 tDIN 0.18 0.18 0.18 0.18 tPY 1.06 1.06 1.06 1.06 tPYS 1.22 1.22 1.22 1.22 tEOUT 0.66 0.66 0.66 0.66 tZL 4.53 3.69 3.69 3.14 tZH 4.15 3.50 3.50 3.03 tLZ 1.80 2.05 2.05 2.22 tHZ 1.70 2.18 2.18 2.48 Units ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-49 * 2.5 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Drive Strength 4 mA 6 mA 8 mA 12 mA Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray.
Speed Grade STD STD STD STD
tDOUT 0.97 0.97 0.97 0.97
tDP 2.41 1.99 1.99 1.77
tDIN 0.18 0.18 0.18 0.18
tPY 1.06 1.06 1.06 1.06
tPYS 1.22 1.22 1.22 1.22
tEOUT 0.66 0.66 0.66 0.66
tZL 2.47 2.04 2.04 1.81
tZH 2.22 1.75 1.75 1.51
tLZ 1.79 2.04 2.04 2.22
tHZ 1.77 2.25 2.25 2.56
Units ns ns ns ns
Applies to 1.2 V DC Core Voltage Table 2-50 * 2.5 LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Drive Strength 4 mA 6 mA 8 mA 12 mA Speed Grade STD STD STD STD tDOUT 0.98 0.98 0.98 0.98 tDP 5.04 4.19 4.19 3.63 tDIN 0.19 0.19 0.19 0.19 tPY 1.19 1.19 1.19 1.19 tPYS 1.40 1.40 1.40 1.40 tEOUT 0.67 0.67 0.67 0.67 tZL 5.12 4.25 4.25 3.69 tZH 4.65 3.98 3.98 3.50 tLZ 2.22 2.48 2.48 2.66 tHZ 2.36 2.85 2.85 3.16 Units ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-51 * 2.5 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Drive Strength 4 mA 6 mA 8 mA 12 mA Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray.
Speed Grade STD STD STD STD
tDOUT 0.98 0.98 0.98 0.98
tDP 2.96 2.52 2.52 2.29
tDIN 0.19 0.19 0.19 0.19
tPY 1.19 1.19 1.19 1.19
tPYS 1.40 1.40 1.40 1.40
tEOUT 0.67 0.67 0.67 0.67
tZL 3.00 2.56 2.56 2.32
tZH 2.67 2.18 2.18 1.94
tLZ 2.22 2.47 2.47 2.65
tHZ 2.46 2.95 2.95 3.27
Units ns ns ns ns
R ev i si o n 1 1
2- 33
IGLOO PLUS DC and Switching Characteristics
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-52 * Minimum and Maximum DC Input and Output Levels 1.8 V LVCMOS Drive Strength Min., V 2 mA 4 mA 6 mA 8 mA Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. 5. Software default selection highlighted in gray.
VIL Max., V
VIH Min., V
VOL Max., V Max., V 3.6 3.6 3.6 3.6 0.45 0.45 0.45 0.45
VOH Min., V VCCI - 0.45 VCCI - 0.45 VCCI - 0.45
IOL IOH
IOSL
IOSH
IIL1 IIH2
mA mA Max., mA3 Max., mA3 A4 A4 2 4 8 2 4 6 8 9 17 35 35 11 22 44 44 10 10 10 10 10 10 10 10
-0.3 -0.3 -0.3 -0.3
0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI
VCCI - 0.45 6
Test Point Datapath 5 pF
R=1k Test Point Enable Path
R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ
Figure 2-9 *
AC Loading
Table 2-53 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) 1.8 Measuring Point* (V) 0.9 CLOAD (pF) 5
* Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.
2- 34
R ev i sio n 1 1
IGLOO PLUS Low Power Flash FPGAs
Timing Characteristics
Applies to 1.5 V DC Core Voltage Table 2-54 * 1.8 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade STD STD STD STD tDOUT 0.97 0.97 0.97 0.97 tDP 5.89 4.82 4.13 4.13 tDIN 0.18 0.18 0.18 0.18 tPY 1.00 1.00 1.00 1.00 tPYS 1.43 1.43 1.43 1.43 tEOUT 0.66 0.66 0.66 0.66 tZL 6.01 4.92 4.21 4.21 tZH 5.43 4.56 3.96 3.96 tLZ 1.78 2.08 2.30 2.30 tHZ 1.30 2.08 2.46 2.46 Units ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-55 * 1.8 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Drive Strength 2 mA 4 mA 6 mA 8 mA Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray.
Speed Grade STD STD STD STD
tDOUT 0.97 0.97 0.97 0.97
tDP 2.82 2.30 2.00 2.00
tDIN 0.18 0.18 0.18 0.18
tPY 1.00 1.00 1.00 1.00
tPYS 1.43 1.43 1.43 1.43
tEOUT 0.66 0.66 0.66 0.66
tZL 2.88 2.35 2.04 2.04
tZH 2.78 2.11 1.76 1.76
tLZ 1.78 2.08 2.29 2.29
tHZ 1.35 2.15 2.55 2.55
Units ns ns ns ns
Applies to 1.2 V DC Core Voltage Table 2-56 * 1.8 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade STD STD STD STD tDOUT 0.98 0.98 0.98 0.98 tDP 6.43 5.33 4.61 4.61 tDIN 0.19 0.19 0.19 0.19 tPY 1.12 1.12 1.12 1.12 tPYS 1.61 1.61 1.61 1.61 tEOUT 0.67 0.67 0.67 0.67 tZL 6.54 5.41 4.69 4.69 tZH 5.93 5.03 4.41 4.41 tLZ 2.19 2.50 2.72 2.72 tHZ 1.88 2.68 3.07 3.07 Units ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-57 * 1.8 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Drive Strength 2 mA 4 mA 6 mA 8 mA Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray.
Speed Grade STD STD STD STD
tDOUT 0.98 0.98 0.98 0.98
tDP 3.30 2.76 2.45 2.45
tDIN 0.19 0.19 0.19 0.19
tPY 1.12 1.12 1.12 1.12
tPYS 1.61 1.61 1.61 1.61
tEOUT 0.67 0.67 0.67 0.67
tZL 3.34 2.79 2.48 2.48
tZH 3.21 2.51 2.16 2.16
tLZ 2.19 2.50 2.71 2.71
tHZ 1.93 2.76 3.16 3.16
Units ns ns ns ns
R ev i si o n 1 1
2- 35
IGLOO PLUS DC and Switching Characteristics
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-58 * Minimum and Maximum DC Input and Output Levels 1.5 V LVCMOS Drive Strength 2 mA 4 mA Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 4. Currents are measured at 85C junction temperature. 5. Software default selection highlighted in gray.
VIL Min. V -0.3 -0.3 Max. V 0.35 * VCCI 0.35 * VCCI Min. V
VIH Max. V 3.6 3.6
VOL Max. V
VOH Min. V
IOL IOH
IOSL
IOSH Max. mA3 16 33
IIL1 IIH2 A4 A4 10 10 10 10
Max. mA mA mA3 2 4 2 4 13 25
0.7 * VCCI 0.7 * VCCI
0.25 * VCCI 0.75 * VCCI 0.25 * VCCI 0.75 * VCCI
Test Point Datapath 5 pF
R=1k Test Point Enable Path
R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ
Figure 2-10 * AC Loading Table 2-59 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) 1.5 Measuring Point* (V) 0.75 CLOAD (pF) 5
* Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.
2- 36
R ev i sio n 1 1
IGLOO PLUS Low Power Flash FPGAs
Timing Characteristics
Applies to 1.5 V DC Core Voltage Table 2-60 * 1.5 V LVCMOS Low Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA 4 mA Speed Grade STD STD tDOUT 0.97 0.97 tDP 6.07 5.24 tDIN 0.18 0.18 tPY 1.16 1.16 tPYS 1.62 1.62 tEOUT 0.66 0.66 tZL 6.19 5.34 tZH 5.53 4.81 tLZ 2.13 2.37 tHZ 2.02 2.47 Units ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-61 * 1.5 V LVCMOS High Slew - Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA 4 mA Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray.
Speed Grade STD STD
tDOUT 0.97 0.97
tDP 2.65 2.29
tDIN 0.18 0.18
tPY 1.16 1.16
tPYS 1.62 1.62
tEOUT 0.66 0.66
tZL 2.71 2.33
tZH 2.43 2.00
tLZ 2.13 2.37
tHZ 2.11 2.57
Units ns ns
Applies to 1.2 V DC Core Voltage Table 2-62 * 1.5 V LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA 4 mA Speed Grade STD STD tDOUT 0.98 0.98 tDP 6.57 5.72 tDIN 0.19 0.19 tPY 1.26 1.26 tPYS 1.80 1.80 tEOUT 0.67 0.67 tZL 6.68 5.81 tZH 6.01 5.27 tLZ 2.54 2.79 tHZ 2.59 3.05 Units ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-63 * 1.5 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA 4 mA Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray.
Speed Grade STD STD
tDOUT 0.98 0.98
tDP 3.08 2.71
tDIN 0.19 0.19
tPY 1.26 1.26
tPYS 1.80 1.80
tEOUT 0.67 0.67
tZL 3.13 2.75
tZH 2.82 2.39
tLZ 2.53 2.78
tHZ 2.68 3.15
Units ns ns
R ev i si o n 1 1
2- 37
IGLOO PLUS DC and Switching Characteristics
1.2 V LVCMOS (JESD8-12A)
Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Table 2-64 * Minimum and Maximum DC Input and Output Levels 1.2 V LVCMOS1 Drive Strength 2 mA Notes:
1. Applicable to IGLOO nano V2 devices operating at VCCI VCC. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 4. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 5. Currents are measured at 85C junction temperature. 6. Software default selection highlighted in gray.
VIL Min. V Max. V Min. V
VIH Max. V 3.6
VOL Max. V
VOH Min. V
IOL IOH mA mA 2 2
IOSL Max. mA4 20
IOSH Max. mA4 26
IIL2 IIH3 A5 A5 10 10
-0.3 0.35 * VCCI 0.65 * VCCI
0.25 * VCCI 0.75 * VCCI
Test Point Datapath 5 pF
R=1k Test Point Enable Path
R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ
Figure 2-11 * AC Loading Table 2-65 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) 1.2 Measuring Point* (V) 0.6 CLOAD (pF) 5
* Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.
Timing Characteristics
Applies to 1.2 V DC Core Voltage Table 2-66 * 1.2 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Drive Strength 2 mA Speed Grade STD tDOUT 0.98 tDP 8.27 tDIN 0.19 tPY 1.57 tPYS 2.34 tEOUT 0.67 tZL 7.94 tZH 6.77 tLZ 3.00 tHZ 3.11 Units ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-67 * 1.2 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Drive Strength 2 mA Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray.
Speed Grade STD
tDOUT 0.98
tDP 3.38
tDIN 0.19
tPY 1.57
tPYS 2.34
tEOUT 0.67
tZL 3.26
tZH 2.78
tLZ 2.99
tHZ 3.24
Units ns
2- 38
R ev i sio n 1 1
IGLOO PLUS Low Power Flash FPGAs
1.2 V LVCMOS Wide Range
Table 2-68 * Minimum and Maximum DC Input and Output Levels 1.2 V LVCMOS Wide Range1 Equivalent Software Default Drive Drive Strength Min. Strength Option2 V 100 A Notes:
1. Applicable to V2 devices only. 2. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 3. IIL is the input leakage current per I/O pin over recommended operation conditions where -0.3 V < VIN < VIL. 4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 5. Currents are measured at high temperature (100C junction temperature) and maximum voltage. 6. Currents are measured at 85C junction temperature. 7. Software default selection highlighted in gray.
VIL
VIH
VOL
VOH
IOL IOH IOSL
IOSH IIL3 IIH4
Max. V
Min. V
Max. V 3.6
Max. V
Min. V
Max. Max mA mA mA5 mA5 A6 A6 2 20 26 10 10
2 mA
-0.3 0.35 * VCCI 0.65 * VCCI
0.25 * VCCI 0.75 * VCCI 2
Table 2-69 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) 1.2 Measuring Point* (V) 0.6 CLOAD (pF) 5
* Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.
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IGLOO PLUS DC and Switching Characteristics
Timing Characteristics
Applies to 1.2 V DC Core Voltage Table 2-70 * 1.2 V LVCMOS Wide Range Low Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Equivalent Software Default Drive Drive Strength Strength Option1 100 A Notes:
1. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Speed Grade STD
tDOUT 0.98
tDP 8.27
tDIN 0.19
tPY 1.57
tPYS 2.34
tEOUT 0.67
tZL 7.94
tZH 6.77
tLZ 3.00
tHZ 3.11
Units ns
2 mA
Table 2-71 * 1.2 V LVCMOS Wide Range High Slew - Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Equivalent Software Default Drive Drive Strength Strength Option1 100 A Notes:
1. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 3. Software default selection highlighted in gray.
Speed Grade STD
tDOUT 0.98
tDP 3.38
tDIN 0.19
tPY 1.57
tPYS 2.34
tEOUT 0.67
tZL 3.26
tZH 2.78
tLZ 2.99
tHZ 3.24
Units ns
2 mA
2- 40
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IGLOO PLUS Low Power Flash FPGAs
I/O Register Specifications
Fully Registered I/O Buffers with Asynchronous Preset
INBUF
Preset
L Pad Out D DOUT Data_out
TRIBUF
PRE D C Q DFN1P1
Data
E
Y Core Array
F D
PRE Q DFN1P1
INBUF CLKBUF
EOUT H I A J D Data Input I/O Register with: Active High Preset Positive-Edge Triggered Data Output Register and Enable Output Register with: Active High Preset Postive-Edge Triggered PRE Q DFN1P1
CLK
CLKBUF
INBUF
CLK
Figure 2-12 * Timing Model of Registered I/O Buffers with Asynchronous Preset
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D_Enable
2- 41
IGLOO PLUS DC and Switching Characteristics Table 2-72 * Parameter Definition and Measuring Nodes Parameter Name tOCLKQ tOSUD tOHD tOPRE2Q tOREMPRE tORECPRE tOECLKQ tOESUD tOEHD tOEPRE2Q tOEREMPRE tOERECPRE tICLKQ tISUD tIHD tIPRE2Q tIREMPRE tIRECPRE Parameter Definition Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Preset Removal Time for the Output Data Register Asynchronous Preset Recovery Time for the Output Data Register Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register Asynchronous Preset Removal Time for the Output Enable Register Asynchronous Preset Recovery Time for the Output Enable Register Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Preset Removal Time for the Input Data Register Asynchronous Preset Recovery Time for the Input Data Register Measuring Nodes (from, to)* H, DOUT F, H F, H L, DOUT L, H L, H H, EOUT J, H J, H I, EOUT I, H I, H A, E C, A C, A D, E D, A D, A
* See Figure 2-12 on page 2-41 for more information.
2- 42
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IGLOO PLUS Low Power Flash FPGAs
Fully Registered I/O Buffers with Asynchronous Clear
Pad Out
DOUT Y D CC Q EE DFN1C1 Data Core Array Data_out FF
TRIBUF INBUF CLKBUF
D
Q
DFN1C1
EOUT CLR LL CLK HH AA JJ DD CLR
INBUF
CLR
D
Q
DFN1C1
Data Input I/O Register with Active High Clear Positive-Edge Triggered
CLR
INBUF
CLKBUF
Data Output Register and Enable Output Register with Active High Clear Positive-Edge Triggered
Figure 2-13 * Timing Model of the Registered I/O Buffers with Asynchronous Clear
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D_Enable
CLK
2- 43
IGLOO PLUS DC and Switching Characteristics Table 2-73 * Parameter Definition and Measuring Nodes Parameter Name tOCLKQ tOSUD tOHD tOCLR2Q tOREMCLR tORECCLR tOECLKQ tOESUD tOEHD tOECLR2Q tOEREMCLR tOERECCLR tICLKQ tISUD tIHD tICLR2Q tIREMCLR tIRECCLR Parameter Definition Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Clear Removal Time for the Output Data Register Asynchronous Clear Recovery Time for the Output Data Register Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Clear Removal Time for the Output Enable Register Asynchronous Clear Recovery Time for the Output Enable Register Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Clear Removal Time for the Input Data Register Asynchronous Clear Recovery Time for the Input Data Register Measuring Nodes (from, to)* HH, DOUT FF, HH FF, HH LL, DOUT LL, HH LL, HH HH, EOUT JJ, HH JJ, HH II, EOUT II, HH II, HH AA, EE CC, AA CC, AA DD, EE DD, AA DD, AA
* See Figure 2-13 on page 2-43 for more information.
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IGLOO PLUS Low Power Flash FPGAs
Input Register
tICKMPWH tICKMPWL 50% 50% tISUD Data 1 50% 0 tIHD 50% tIWPRE Preset 50% tIRECPRE 50% tIWCLR Clear tIPRE2Q Out_1 50% tICLKQ 50% tICLR2Q 50% 50% tIRECCLR 50% tIREMPRE 50% tIREMCLR 50% 50% 50% 50% 50% 50%
CLK
Figure 2-14 * Input Register Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage Table 2-74 * Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tICLKQ tISUD tIHD tICLR2Q tIPRE2Q tIREMCLR tIRECCLR tIREMPRE tIRECPRE tIWCLR tIWPRE tICKMPWH tICKMPWL Description Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Clear Removal Time for the Input Data Register Asynchronous Clear Recovery Time for the Input Data Register Asynchronous Preset Removal Time for the Input Data Register Asynchronous Preset Recovery Time for the Input Data Register Asynchronous Clear Minimum Pulse Width for the Input Data Register Asynchronous Preset Minimum Pulse Width for the Input Data Register Clock Minimum Pulse Width High for the Input Data Register Clock Minimum Pulse Width Low for the Input Data Register Std. 0.41 0.32 0.00 0.57 0.57 0.00 0.24 0.00 0.24 0.19 0.19 0.31 0.28 Units ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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IGLOO PLUS DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-75 * Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter tICLKQ tISUD tIHD tICLR2Q tIPRE2Q tIREMCLR tIRECCLR tIREMPRE tIRECPRE tIWCLR tIWPRE tICKMPWH tICKMPWL Description Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Clear Removal Time for the Input Data Register Asynchronous Clear Recovery Time for the Input Data Register Asynchronous Preset Removal Time for the Input Data Register Asynchronous Preset Recovery Time for the Input Data Register Asynchronous Clear Minimum Pulse Width for the Input Data Register Asynchronous Preset Minimum Pulse Width for the Input Data Register Clock Minimum Pulse Width High for the Input Data Register Clock Minimum Pulse Width Low for the Input Data Register Std. 0.66 0.43 0.00 0.86 0.86 0.00 0.24 0.00 0.24 0.19 0.19 0.31 0.28 Units ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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IGLOO PLUS Low Power Flash FPGAs
Output Register
tOCKMPWH tOCKMPWL 50% 50% tOSUD tOHD Data_out 1 50% 0 50% tOWPRE Preset 50% tORECPRE 50% tOREMPRE 50% tOREMCLR 50% 50% 50% 50% 50% 50%
CLK
tOWCLR Clear tOPRE2Q DOUT 50% tOCLKQ 50% tOCLR2Q 50% 50%
tORECCLR
50%
Figure 2-15 * Output Register Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage Table 2-76 * Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tOCLKQ tOSUD tOHD tOCLR2Q tOPRE2Q tOREMCLR tORECCLR tOREMPRE tORECPRE tOWCLR tOWPRE tOCKMPWH tOCKMPWL Description Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Clear Removal Time for the Output Data Register Asynchronous Clear Recovery Time for the Output Data Register Asynchronous Preset Removal Time for the Output Data Register Asynchronous Preset Recovery Time for the Output Data Register Asynchronous Clear Minimum Pulse Width for the Output Data Register Asynchronous Preset Minimum Pulse Width for the Output Data Register Clock Minimum Pulse Width High for the Output Data Register Clock Minimum Pulse Width Low for the Output Data Register Std. 0.66 0.33 0.00 0.82 0.88 0.00 0.24 0.00 0.24 0.19 0.19 0.31 0.28 Units ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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IGLOO PLUS DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-77 * Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter tOCLKQ tOSUD tOHD tOCLR2Q tOPRE2Q tOREMCLR tORECCLR tOREMPRE tORECPRE tOWCLR tOWPRE tOCKMPWH tOCKMPWL Description Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Clear Removal Time for the Output Data Register Asynchronous Clear Recovery Time for the Output Data Register Asynchronous Preset Removal Time for the Output Data Register Asynchronous Preset Recovery Time for the Output Data Register Asynchronous Clear Minimum Pulse Width for the Output Data Register Asynchronous Preset Minimum Pulse Width for the Output Data Register Clock Minimum Pulse Width High for the Output Data Register Clock Minimum Pulse Width Low for the Output Data Register Std. 1.03 0.52 0.00 1.22 1.31 0.00 0.24 0.00 0.24 0.19 0.19 0.31 0.28 Units ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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IGLOO PLUS Low Power Flash FPGAs
Output Enable Register
tOECKMPWH tOECKMPWL
50% CLK
50% tOESUD tOEHD
50%
50%
50%
50%
50%
D_Enable
1
50%
0 50% tOEWPRE 50% tOEREMPRE 50%
tOERECPRE 50%
Preset tOEWCLR 50% Clear tOEPRE2Q 50% EOUT tOECLKQ 50% tOECLR2Q 50% tOERECCLR 50% tOEREMCLR 50%
Figure 2-16 * Output Enable Register Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage Table 2-78 * Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tOECLKQ tOESUD tOEHD tOECLR2Q tOEPRE2Q tOEREMCLR tOERECCLR tOEREMPRE tOERECPRE tOEWCLR tOEWPRE tOECKMPWH tOECKMPWL Description Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register Asynchronous Clear Removal Time for the Output Enable Register Asynchronous Clear Recovery Time for the Output Enable Register Asynchronous Preset Removal Time for the Output Enable Register Asynchronous Preset Recovery Time for the Output Enable Register Asynchronous Clear Minimum Pulse Width for the Output Enable Register Asynchronous Preset Minimum Pulse Width for the Output Enable Register Clock Minimum Pulse Width High for the Output Enable Register Clock Minimum Pulse Width Low for the Output Enable Register Std. 0.68 0.33 0.00 0.84 0.91 0.00 0.24 0.00 0.24 0.19 0.19 0.31 0.28 Units ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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IGLOO PLUS DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-79 * Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter tOECLKQ tOESUD tOEHD tOECLR2Q tOEPRE2Q tOEREMCLR tOERECCLR tOEREMPRE tOERECPRE tOEWCLR tOEWPRE tOECKMPWH tOECKMPWL Description Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register Asynchronous Clear Removal Time for the Output Enable Register Asynchronous Clear Recovery Time for the Output Enable Register Asynchronous Preset Removal Time for the Output Enable Register Asynchronous Preset Recovery Time for the Output Enable Register Asynchronous Clear Minimum Pulse Width for the Output Enable Register Asynchronous Preset Minimum Pulse Width for the Output Enable Register Clock Minimum Pulse Width High for the Output Enable Register Clock Minimum Pulse Width Low for the Output Enable Register Std. 1.06 0.52 0.00 1.25 1.36 0.00 0.24 0.00 0.24 0.19 0.19 0.31 0.28 Units ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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IGLOO PLUS Low Power Flash FPGAs
VersaTile Characteristics
VersaTile Specifications as a Combinatorial Module
The IGLOO PLUS library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/ E Macro Library Guide.
A
INV
Y
A OR2 B A AND2 B Y Y
A NOR2 B Y
A NAND2 B A B C Y
A B XOR2 Y
XOR3
Y
A A B C B C
MAJ3 Y
A 0 MUX2 B 1 Y
NAND3
S
Figure 2-17 * Sample of Combinatorial Cells
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IGLOO PLUS DC and Switching Characteristics
tPD Fanout = 4 Net Length = 1 VersaTile B A NAND2 or Any Combinatorial Logic Y
Net Length = 1 VersaTile
A NAND2 or Any Combinatorial Logic
tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for a particular combinatorial cell Y
B Net Length = 1 VersaTile B A A
NAND2 or Any Combinatorial Logic
Y
Net Length = 1 VersaTile
B
VCC
NAND2 or Any Combinatorial Logic
Y
50% A, B, C
50% GND VCC
50% OUT GND VCC OUT 50% tPD (RF) GND tPD (RR) tPD (FF) tPD (FR)
50%
50%
Figure 2-18 * Timing Model and Waveforms
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IGLOO PLUS Low Power Flash FPGAs
Timing Characteristics
1.5 V DC Core Voltage
Table 2-80 * Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Combinatorial Cell INV AND2 NAND2 OR2 NOR2 XOR2 MAJ3 XOR3 MUX2 AND3 Equation Y = !A Y=A*B Y = !(A * B) Y=A+B Y = !(A + B) Y=AB Y = MAJ(A, B, C) Y=ABC Y = A !S + B S Y=A*B*C Parameter tPD tPD tPD tPD tPD tPD tPD tPD tPD tPD Std. 0.72 0.86 1.00 1.26 1.16 1.46 1.47 2.12 1.24 1.40 Units ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
1.2 V DC Core Voltage
Table 2-81 * Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Combinatorial Cell INV AND2 NAND2 OR2 NOR2 XOR2 MAJ3 XOR3 MUX2 AND3 Equation Y = !A Y=A*B Y = !(A * B) Y=A+B Y = !(A + B) Y=AB Y = MAJ(A, B, C) Y=ABC Y = A !S + B S Y=A*B*C Parameter tPD tPD tPD tPD tPD tPD tPD tPD tPD tPD Std. 1.26 1.46 1.78 2.47 2.17 2.62 2.66 3.77 2.20 2.49 Units ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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IGLOO PLUS DC and Switching Characteristics
VersaTile Specifications as a Sequential Module
The IGLOO PLUS library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E Macro Library Guide.
Data
D DFN1
Q
Out
Data D En CLK Q
Out
DFN1E1
CLK
PRE
Data
D
Q DFN1C1
Out
Data En CLK
D
Q
Out
DFI1E1P1
CLK CLR
Figure 2-19 * Sample of Sequential Cells
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IGLOO PLUS Low Power Flash FPGAs
tCKMPWH tCKMPWL 50% tSUD Data 50% tHD 0 50% 50% 50% 50% 50% 50%
CLK
50%
EN 50% tHE PRE tSUE 50% tWPRE tRECPRE 50% tREMPRE 50% tREMCLR 50%
tWCLR CLR tPRE2Q Out tCLKQ 50% 50% 50%
tRECCLR 50%
tCLR2Q 50%
Figure 2-20 * Timing Model and Waveforms
Timing Characteristics
1.5 V DC Core Voltage
Table 2-82 * Register Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tCLKQ tSUD tHD tSUE tHE tCLR2Q tPRE2Q tREMCLR tRECCLR tREMPRE tRECPRE tWCLR tWPRE tCKMPWH tCKMPWL Clock-to-Q of the Core Register Data Setup Time for the Core Register Data Hold Time for the Core Register Enable Setup Time for the Core Register Enable Hold Time for the Core Register Asynchronous Clear-to-Q of the Core Register Asynchronous Preset-to-Q of the Core Register Asynchronous Clear Removal Time for the Core Register Asynchronous Clear Recovery Time for the Core Register Asynchronous Preset Removal Time for the Core Register Asynchronous Preset Recovery Time for the Core Register Asynchronous Clear Minimum Pulse Width for the Core Register Asynchronous Preset Minimum Pulse Width for the Core Register Clock Minimum Pulse Width High for the Core Register Clock Minimum Pulse Width Low for the Core Register Description Std. 0.89 0.81 0.00 0.73 0.00 0.60 0.62 0.00 0.24 0.00 0.23 0.30 0.30 0.56 0.56 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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IGLOO PLUS DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-83 * Register Delays Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter tCLKQ tSUD tHD tSUE tHE tCLR2Q tPRE2Q tREMCLR tRECCLR tREMPRE tRECPRE tWCLR tWPRE tCKMPWH tCKMPWL Clock-to-Q of the Core Register Data Setup Time for the Core Register Data Hold Time for the Core Register Enable Setup Time for the Core Register Enable Hold Time for the Core Register Asynchronous Clear-to-Q of the Core Register Asynchronous Preset-to-Q of the Core Register Asynchronous Clear Removal Time for the Core Register Asynchronous Clear Recovery Time for the Core Register Asynchronous Preset Removal Time for the Core Register Asynchronous Preset Recovery Time for the Core Register Asynchronous Clear Minimum Pulse Width for the Core Register Asynchronous Preset Minimum Pulse Width for the Core Register Clock Minimum Pulse Width High for the Core Register Clock Minimum Pulse Width Low for the Core Register Description Std. 1.61 1.17 0.00 1.29 0.00 0.87 0.89 0.00 0.24 0.00 0.24 0.46 0.46 0.95 0.95 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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IGLOO PLUS Low Power Flash FPGAs
Global Resource Characteristics
AGLP125 Clock Tree Topology
Clock delays are device-specific. Figure 2-21 is an example of a global tree used for clock routing. The global tree presented in Figure 2-21 is driven by a CCC located on the west side of the AGLP125 device. It is used to drive all D-flip-flops in the device.
Central Global Rib
CCC
VersaTile Rows
Global Spine
Figure 2-21 * Example of Global Tree Use in an AGLP125 Device for Clock Routing
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IGLOO PLUS DC and Switching Characteristics
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard-dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-61. Table 2-84 to Table 2-89 on page 2-60 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading.
Timing Characteristics
1.5 V DC Core Voltage Table 2-84 * AGLP030 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
1
Description Input Low Delay for Global Clock Input High Delay for Global Clock Minimum Pulse Width High for Global Clock Minimum Pulse Width Low for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
Min.
Max.2 1.42 1.49
Units ns ns ns ns
1.21 1.23
0.27
ns MHz
Table 2-85 * AGLP060 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
1
Description Input Low Delay for Global Clock Input High Delay for Global Clock Minimum Pulse Width High for Global Clock Minimum Pulse Width Low for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
Min.
Max.2 1.62 1.72
Units ns ns ns ns
1.32 1.34
0.38
ns MHz
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IGLOO PLUS Low Power Flash FPGAs Table 2-86 * AGLP125 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
1
Description Input Low Delay for Global Clock Input High Delay for Global Clock Minimum Pulse Width High for Global Clock Minimum Pulse Width Low for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
Min.
Max.2 1.71 1.82
Units ns ns ns ns
1.36 1.39
0.43
ns MHz
1.2 V DC Core Voltage Table 2-87 * AGLP030 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Description Input Low Delay for Global Clock Input High Delay for Global Clock Minimum Pulse Width High for Global Clock Minimum Pulse Width Low for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
Min.1 1.80 1.88
Max.2 2.09 2.27
Units ns ns ns ns
0.39
ns MHz
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IGLOO PLUS DC and Switching Characteristics Table 2-88 * AGLP060 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
1
Description Input Low Delay for Global Clock Input High Delay for Global Clock Minimum Pulse Width High for Global Clock Minimum Pulse Width Low for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
Min.
Max.2 2.43 2.65
Units ns ns ns ns
2.02 2.09
0.56
ns MHz
Table 2-89 * AGLP125 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Description Input Low Delay for Global Clock Input High Delay for Global Clock Minimum Pulse Width High for Global Clock Minimum Pulse Width Low for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
Min.1 2.08 2.15
Max.2 2.54 2.77
Units ns ns ns ns
0.62
ns MHz
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IGLOO PLUS Low Power Flash FPGAs
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-90 * IGLOO PLUS CCC/PLL Specification For IGLOO PLUS V2 or V5 devices, 1.5 V DC Core Supply Voltage Parameter Clock Conditioning Circuitry Input Frequency fIN_CCC Clock Conditioning Circuitry Output Frequency fOUT_CCC Delay Increments in Programmable Delay Blocks PLL3,4 100 MHz
1, 2
Min. 1.5 0.75
Typ.
Max. 250 250
Units MHz MHz ps
360 32
Number of Programmable Values in Each Programmable Delay Block Serial Clock (SCLK) for Dynamic
Input Cycle-to-Cycle Jitter (peak magnitude) Acquisition Time LockControl = 0 LockControl = 1 Tracking Jitter5 LockControl = 0 LockControl = 1 Output Duty Cycle Delay Range in Block: Programmable Delay
1, 2
300 6.0
s ms
2.5 1.5 48.5 51.5 15.65 15.65 3.5 ns % ns ns ns SSO 8 0.80% 6.00% SSO 16 1.20% 12.00%
1 1, 2
1, 2
1.25 0.469
Delay Range in Block: Programmable Delay 2 Delay Range in Block: Fixed Delay
VCO Output Peak-to-Peak Period Jitter
FCCC_OUT6
Maximum Peak-to-Peak Period Jitter6,7,8 SSO 2 SSO 4 0.60% 4.00%
0.75 MHz to 50 MHz 50 MHz to 250 MHz Notes:
0.50% 2.50%
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings. 2. TJ = 25C, VCC = 1.5 V 3. Maximum value obtained for a STD speed grade device in Worst Case Commercial Conditions. For specific junction temperature and voltage supply, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for derating values. 4. The AGLP030 device does not support a PLL. 5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter. 6. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying the VCO period by the per cent jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output divider settings. 7. Measurements done with LVTTL 3.3 V 8 mA I/O drive strength and high slew rate, VCC/VCCPLL = 1.14 V, VCCI = 3.3 V, VQ/PQ/TQ type of packages, 20 pF load. 8. SSO are outputs that are synchronous to a single clock domain and have clock-to-out times that are within 200 ps of each other.Switching I/Os are placed outside of the PLL bank. Refer to the "ProASIC3/E SSO and Pin Placement Guidelines" chapter of the ProASIC3 FPGA Fabric User's Guide.
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IGLOO PLUS DC and Switching Characteristics Table 2-91 * IGLOO PLUS CCC/PLL Specification For IGLOO PLUS V2 Devices, 1.2 V DC Core Supply Voltage Parameter Clock Conditioning Circuitry Input Frequency fIN_CCC Clock Conditioning Circuitry Output Frequency fOUT_CCC Delay Increments in Programmable Delay Blocks
3,4 1, 2
Min. 1.5 0.75
Typ.
Max. 160 160
Units MHz MHz ps
580 32
Number of Programmable Values in Each Programmable Delay Block Serial Clock (SCLK) for Dynamic PLL
Input Cycle-to-Cycle Jitter (peak magnitude) Acquisition Time LockControl = 0 LockControl = 1 Tracking Jitter
5
60
MHz
300 6.0
s ms
LockControl = 0 LockControl = 1 Output Duty Cycle Delay Range in Block: Programmable Delay 1 Delay Range in Block: Programmable Delay 2 Delay Range in Block: Fixed Delay 1, 2 VCO Output Peak-to-Peak Period Jitter FCCC_OUT6 SSO 2 0.75 MHz to 50 MHz 50 MHz to 160 MHz Notes: 0.50% 2.50%
1, 2 1, 2
4 3 48.5 2.3 0.025 5.7 SSO 4 1.20% 5.00% SSO 8 2.00% 7.00% 51.5 20.86 20.86
ns ns % ns ns ns SSO 16 3.00% 15.00%
Maximum Peak-to-Peak Period Jitter6,7,8
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings. 2. TJ = 25C, VCC = 1.2 V 3. Maximum value obtained for a STD speed grade device in Worst Case Commercial Conditions.For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for derating values. 4. The AGLP030 device does not support PLL. 5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter. 6. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying the VCO period by the per cent jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output divider settings. 7. Measurements are done with LVTTL 3.3 V, 8 mA, I/O drive strength and high slew rate. VCC/VCCPLL = 1.14 V, VCCI = 3.3 V, VQ/PQ/TQ type of packages, 20 pF load. 8. SSO are outputs that are synchronous to a single clock domain, and have their clock-to-out times within 200 ps of each other. Switching I/Os are placed outside of the PLL bank. Refer to the "ProASIC3/E SSO and Pin Placement Guidelines" chapter of the ProASIC3 FPGA Fabric User's Guide.
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Output Signal
Tperiod_max
Tperiod_min
Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max - Tperiod_min. Figure 2-22 * Peak-to-Peak Jitter Definition
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IGLOO PLUS DC and Switching Characteristics
Embedded SRAM and FIFO Characteristics
SRAM
RAM4K9 ADDRA11 ADDRA10 ADDRA0 DINA8 DINA7 DOUTA8 DOUTA7 DOUTA0 RAM512X18 RADDR8 RADDR7 RADDR0 RD17 RD16 RD0
DINA0
RW1 RW0
WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 ADDRB10 ADDRB0 DINB8 DINB7 DOUTB8 DOUTB7 DOUTB0
PIPE
REN RCLK WADDR8 WADDR7
WADDR0 WD17 WD16
WD0 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB RESET WW1 WW0
WEN WCLK RESET
Figure 2-23 * RAM Models
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Timing Waveforms
tCYC tCKH CLK tAS ADD A0 tBKS BLK_B tENS WEN_B tCKQ1 DO Dn D0 tDOH1
Figure 2-24 * RAM Read for Pass-Through Output
tCKL
tAH A1 A2 tBKH tENH
D1
D2
tCYC tCKH CLK t ADD tBKS BLK_B tENS WEN_B tCKQ2 DO Dn D0 tDOH2
Figure 2-25 * RAM Read for Pipelined Output
AS
tCKL
tAH A0 A1 A2 tBKH tENH
D1
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IGLOO PLUS DC and Switching Characteristics
tCYC tCKH CLK tAS ADD A0 tBKS tBKH BLK_B tENS WEN_B tDS DI DI0 tDH DI1 tENH tAH A1 A2 tCKL
DO
Dn
D2
Figure 2-26 * RAM Write, Output Retained (WMODE = 0)
tCYC tCKH CLK tAS ADD A0 tBKS BLK_B tENS WEN_B tDS DI DO (pass-through) DO (pipelined) DI0 tDH DI1 DI2 tBKH tAH A1 A2 tCKL
Dn
DI0
DI1
Dn
DI0
DI1
Figure 2-27 * RAM Write, Output as Write Data (WMODE = 1)
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CLK1 tAS ADD1 WEN_B1 tCKQ1 DO1 (pass-through) DO1 (pipelined) CLK2 tAS ADD2 A0 D1 tAH A1 D2 A3 D3 Dn D0 tCKQ2 Dn tCCKH D0 tCKQ1 D1 tAH A0 A1 A0
DI2 WEN_B2
Figure 2-28 * Write Access after Read onto Same Address
tCYC tCKH CLK tCKL
RESET_B tRSTBQ DO Dm Dn
Figure 2-29 * RAM Reset
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IGLOO PLUS DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-92 * RAM4K9 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tAS tAH tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tC2CWWL tC2CRWH tC2CWRH tRSTBQ tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX Address setup time Address hold time REN_B, WEN_B setup time REN_B, WEN_B hold time BLK_B setup time BLK_B hold time Input data (DI) setup time Input data (DI) hold time Clock High to new data valid on DO (output retained, WMODE = 0) Clock High to new data valid on DO (flow-through, WMODE = 1) Clock High to new data valid on DO (pipelined) Description Std. Units 0.69 0.13 0.68 0.13 1.37 0.13 0.59 0.30 2.94 2.55 1.51 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Address collision clk-to-clk delay for reliable write after write on same address - applicable 0.29 to closing edge Address collision clk-to-clk delay for reliable read access after write on same address - 0.24 applicable to opening edge Address collision clk-to-clk delay for reliable write access after read on same address - 0.40 applicable to opening edge RESET_B Low to data out Low on DO (flow-through) RESET_B Low to data out Low on DO (pipelined) RESET_B removal RESET_B recovery RESET_B minimum pulse width Clock cycle time Maximum frequency 1.72 1.72 0.51 2.68 0.68 6.24 160
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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IGLOO PLUS Low Power Flash FPGAs Table 2-93 * RAM512X18 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tAS tAH tENS tENH tDS tDH tCKQ1 tCKQ2 tC2CRWH tC2CWRH tRSTBQ tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX Address setup time Address hold time REN_B, WEN_B setup time REN_B, WEN_B hold time Input data (DI) setup time Input data (DI) hold time Clock High to new data valid on DO (output retained, WMODE = 0) Clock High to new data valid on DO (pipelined) Description Std. Units 0.69 0.13 0.61 0.07 0.59 0.30 3.51 1.43 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Address collision clk-to-clk delay for reliable read access after write on same address - 0.21 applicable to opening edge Address collision clk-to-clk delay for reliable write access after read on same address - 0.25 applicable to opening edge RESET_B Low to data out Low on DO (flow-through) RESET_B Low to data out Low on DO (pipelined) RESET_B removal RESET_B recovery RESET_B minimum pulse width Clock cycle time Maximum frequency 1.72 1.72 0.51 2.68 0.68 6.24 160
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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IGLOO PLUS DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-94 * RAM4K9 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter tAS tAH tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tC2CWWL tC2CRWH tC2CWRH tRSTBQ tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX Address setup time Address hold time REN_B, WEN_B setup time REN_B, WEN_B hold time BLK_B setup time BLK_B hold time Input data (DI) setup time Input data (DI) hold time Clock High to new data valid on DO (output retained, WMODE = 0) Clock High to new data valid on DO (flow-through, WMODE = 1) Clock High to new data valid on DO (pipelined) Address collision clk-to-clk delay for reliable write after write on same address - applicable to closing edge Address collision clk-to-clk delay for reliable read access after write on same address - applicable to opening edge Address collision clk-to-clk delay for reliable write access after read on same address - applicable to opening edge RESET_B Low to data out Low on DO (flow-through) RESET_B Low to data out Low on DO (pipelined) RESET_B removal RESET_B recovery RESET_B minimum pulse width Clock cycle time Maximum frequency Description Std. 1.28 0.25 1.25 0.25 2.54 0.25 1.10 0.55 5.51 4.77 2.82 0.30 0.32 0.44 3.21 3.21 0.93 4.94 1.18 10.90 92 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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IGLOO PLUS Low Power Flash FPGAs Table 2-95 * RAM512X18 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter tAS tAH tENS tENH tDS tDH tCKQ1 tCKQ2 tC2CRWH tC2CWRH tRSTBQ tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX Address setup time Address hold time REN_B, WEN_B setup time REN_B, WEN_B hold time Input data (DI) setup time Input data (DI) hold time Clock High to new data valid on DO (output retained, WMODE = 0) Clock High to new data valid on DO (pipelined) Address collision clk-to-clk delay for reliable read access after write on same address - applicable to opening edge Address collision clk-to-clk delay for reliable write access after read on same address - applicable to opening edge RESET_B Low to data out Low on DO (flow through) RESET_B Low to data out Low on DO (pipelined) RESET_B removal RESET_B recovery RESET_B minimum pulse width Clock cycle time Maximum frequency Description Std. 1.28 0.25 1.13 0.13 1.10 0.55 6.56 2.67 0.29 0.36 3.21 3.21 0.93 4.94 1.18 10.90 92 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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IGLOO PLUS DC and Switching Characteristics
FIFO
FIFO4K18 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP AEVAL11 AEVAL10 RD17 RD16
RD0 FULL AFULL EMPTY AEMPTY
AEVAL0 AFVAL11 AFVAL10
AFVAL0 REN RBLK RCLK WD17 WD16
WD0 WEN WBLK WCLK RPIPE
RESET
Figure 2-30 * FIFO Model
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Timing Waveforms
RCLK/ WCLK tMPWRSTB RESET_B tRSTFG EMPTY tRSTAF AEMPTY tRSTFG FULL tRSTAF AFULL WA/RA (Address Counter)
Figure 2-31 * FIFO Reset
tRSTCK
MATCH (A0)
tCYC RCLK tRCKEF EMPTY tCKAF AEMPTY WA/RA (Address Counter) NO MATCH
NO MATCH
Dist = AEF_TH
MATCH (EMPTY)
Figure 2-32 * FIFO EMPTY Flag and AEMPTY Flag Assertion
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IGLOO PLUS DC and Switching Characteristics
tCYC WCLK tWCKFF FULL tCKAF AFULL
WA/RA NO MATCH (Address Counter)
NO MATCH
Dist = AFF_TH
MATCH (FULL)
Figure 2-33 * FIFO FULL Flag and AFULL Flag Assertion
WCLK
WA/RA (Address Counter)
MATCH (EMPTY)
NO MATCH
NO MATCH 2nd Rising Edge After 1st Write tRCKEF
NO MATCH
NO MATCH
Dist = AEF_TH + 1
RCLK
1st Rising Edge After 1st Write
EMPTY tCKAF AEMPTY
Figure 2-34 * FIFO EMPTY Flag and AEMPTY Flag Deassertion
RCLK WA/RA (Address Counter)
MATCH (FULL) NO MATCH NO MATCH NO MATCH NO MATCH Dist = AFF_TH - 1
WCLK
1st Rising Edge After 1st Read
1st Rising Edge After 2nd Read tWCKF
FULL tCKAF AFULL
Figure 2-35 * FIFO FULL Flag and AFULL Flag Deassertion
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Timing Characteristics
1.5 V DC Core Voltage
Table 2-96 * FIFO Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tRCKEF tWCKFF tCKAF tRSTFG tRSTAF tRSTBQ tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time BLK_B Setup Time BLK_B Hold Time Input Data (DI) Setup Time Input Data (DI) Hold Time Clock High to New Data Valid on DO (flow-through) Clock High to New Data Valid on DO (pipelined) RCLK High to Empty Flag Valid WCLK High to Full Flag Valid Clock High to Almost Empty/Full Flag Valid RESET_B Low to Empty/Full Flag Valid RESET_B Low to Almost Empty/Full Flag Valid RESET_B Low to Data Out Low on DO (flow-through) RESET_B Low to Data Out Low on DO (pipelined) RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency for FIFO Description Std. 1.66 0.13 0.30 0.00 0.63 0.20 2.77 1.50 2.94 2.79 10.71 2.90 10.60 1.68 1.68 0.51 2.68 0.68 6.24 160 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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IGLOO PLUS DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-97 * FIFO Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V Parameter tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tRCKEF tWCKFF tCKAF tRSTFG tRSTAF tRSTBQ tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time BLK_B Setup Time BLK_B Hold Time Input Data (DI) Setup Time Input Data (DI) Hold Time Clock High to New Data Valid on DO (flow-through) Clock High to New Data Valid on DO (pipelined) RCLK High to Empty Flag Valid WCLK High to Full Flag Valid Clock High to Almost Empty/Full Flag Valid RESET_B Low to Empty/Full Flag Valid RESET_B Low to Almost Empty/Full Flag Valid RESET_B Low to Data Out Low on DO (flow-through) RESET_B Low to Data Out Low on DO (pipelined) RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency for FIFO Description Std. 3.44 0.26 0.30 0.00 1.30 0.41 5.67 3.02 6.02 5.71 22.17 5.93 21.94 3.41 3.41 1.02 5.48 1.18 10.90 92 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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Embedded FlashROM Characteristics
tSU CLK tHOLD tSU tHOLD tSU tHOLD
Address
A0 tCKQ2
A1 tCKQ2 D0 tCKQ2 D1
Data
D0
Figure 2-36 * Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-98 * Embedded FlashROM Access Time Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V Parameter tSU tHOLD tCK2Q FMAX Address Setup Time Address Hold Time Clock to Out Maximum Clock Frequency Description Std. 0.57 0.00 17.58 15 Units ns ns ns MHz
1.2 V DC Core Voltage
Table 2-99 * Embedded FlashROM Access Time Worst Commercial-Case Conditions: TJ = 70C, VCC = 1.14 V Parameter tSU tHOLD tCK2Q FMAX Address Setup Time Address Hold Time Clock to Out Maximum Clock Frequency Description Std. 0.59 0.00 30.94 10 Units ns ns ns MHz
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IGLOO PLUS DC and Switching Characteristics
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-15 for more details.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-100 * JTAG 1532 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V Parameter tDISU tDIHD tTMSSU tTMDHD tTCK2Q tRSTB2Q FTCKMAX tTRSTREM tTRSTREC tTRSTMPW Description Test Data Input Setup Time Test Data Input Hold Time Test Mode Select Setup Time Test Mode Select Hold Time Clock to Q (data out) Reset to Q (data out) TCK Maximum Frequency ResetB Removal Time ResetB Recovery Time ResetB Minimum Pulse Std. 1.00 2.00 1.00 2.00 8.00 25.00 15 0.58 0.00 TBD Units ns ns ns ns ns ns MHz ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
1.2 V DC Core Voltage
Table 2-101 * JTAG 1532 Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V Parameter tDISU tDIHD tTMSSU tTMDHD tTCK2Q tRSTB2Q FTCKMAX tTRSTREM tTRSTREC tTRSTMPW Description Test Data Input Setup Time Test Data Input Hold Time Test Mode Select Setup Time Test Mode Select Hold Time Clock to Q (data out) Reset to Q (data out) TCK Maximum Frequency ResetB Removal Time ResetB Recovery Time ResetB Minimum Pulse Std. 1.50 3.00 1.50 3.00 11.00 30.00 9.00 1.18 0.00 TBD Units ns ns ns ns ns ns MHz ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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Actel Safety Critical, Life Support, and High-Reliability Applications Policy
The Actel products described in this advance status datasheet may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information.
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IGLOO PLUS Low Power Flash FPGAs
3 - Package Pin Assignments
128-Pin VQFP
128 1
128-Pin VQFP
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. Pin information is in the "Pin Descriptions" chapter of the IGLOO PLUS FPGA Fabric User's Guide.
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3 -1
Package Pin Assignments
128-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 AGLP030 Function IO119RSB3 IO118RSB3 IO117RSB3 IO115RSB3 IO116RSB3 IO113RSB3 IO114RSB3 GND VCCIB3 IO112RSB3 IO111RSB3 IO110RSB3 IO109RSB3 GEC0/IO108RSB3 GEA0/IO107RSB3 GEB0/IO106RSB3 VCC IO104RSB3 IO103RSB3 IO102RSB3 IO101RSB3 IO100RSB3 IO99RSB3 GND VCCIB3 IO97RSB3 IO98RSB3 IO95RSB3 IO96RSB3 IO94RSB3 IO93RSB3 IO92RSB3 IO91RSB2 FF/IO90RSB2 IO89RSB2
128-Pin VQFP Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 AGLP030 Function IO88RSB2 IO86RSB2 IO84RSB2 IO83RSB2 GND VCCIB2 IO82RSB2 IO81RSB2 IO79RSB2 IO78RSB2 IO77RSB2 IO75RSB2 IO74RSB2 VCC IO73RSB2 IO72RSB2 IO70RSB2 IO69RSB2 IO68RSB2 IO66RSB2 IO65RSB2 GND VCCIB2 IO63RSB2 IO61RSB2 IO59RSB2 TCK TDI TMS VPUMP TDO TRST IO58RSB1 VJTAG IO56RSB1
128-Pin VQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 AGLP030 Function IO57RSB1 VCCIB1 GND IO55RSB1 IO54RSB1 IO53RSB1 IO52RSB1 IO51RSB1 IO50RSB1 IO49RSB1 VCC GDB0/IO48RSB1 GDA0/IO47RSB1 GDC0/IO46RSB1 IO45RSB1 IO44RSB1 IO43RSB1 IO42RSB1 VCCIB1 GND IO40RSB1 IO41RSB1 IO39RSB1 IO38RSB1 IO37RSB1 IO36RSB1 IO35RSB0 IO34RSB0 IO33RSB0 IO32RSB0 IO30RSB0 IO28RSB0 IO27RSB0 VCCIB0 GND
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IGLOO PLUS Low Power Flash FPGAs
128-Pin VQFP Pin Number 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 AGLP030 Function IO26RSB0 IO25RSB0 IO23RSB0 IO22RSB0 IO21RSB0 IO19RSB0 IO18RSB0 VCC IO17RSB0 IO16RSB0 IO14RSB0 IO13RSB0 IO12RSB0 IO10RSB0 IO09RSB0 VCCIB0 GND IO07RSB0 IO05RSB0 IO03RSB0 IO02RSB0 IO01RSB0 IO00RSB0
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Package Pin Assignments
176-Pin VQFP
1176
176-Pin VQFP
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx.
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IGLOO PLUS Low Power Flash FPGAs
176-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 AGLP060 Function GAA2/IO156RSB3 IO155RSB3 GAB2/IO154RSB3 IO153RSB3 GAC2/IO152RSB3 GND VCCIB3 IO149RSB3 IO147RSB3 IO145RSB3 IO144RSB3 IO143RSB3 VCC IO141RSB3 GFC1/IO140RSB3 GFB1/IO138RSB3 GFB0/IO137RSB3 VCOMPLF GFA1/IO136RSB3 VCCPLF GFA0/IO135RSB3 GND VCCIB3 GFA2/IO134RSB3 GFB2/IO133RSB3 GFC2/IO132RSB3 IO131RSB3 IO130RSB3 IO129RSB3 IO127RSB3 IO126RSB3 IO125RSB3 IO123RSB3 IO122RSB3 IO121RSB3 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
176-Pin VQFP Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 AGLP060 Function IO119RSB3 GND VCCIB3 GEC1/IO116RSB3 GEB1/IO114RSB3 GEC0/IO115RSB3 GEB0/IO113RSB3 GEA1/IO112RSB3 GEA0/IO111RSB3 GEA2/IO110RSB2 NC FF/GEB2/IO109R SB2 GEC2/IO108RSB2 IO106RSB2 IO107RSB2 IO104RSB2 IO105RSB2 IO102RSB2 IO103RSB2 GND VCCIB2 IO101RSB2 IO100RSB2 IO99RSB2 IO98RSB2 IO97RSB2 IO96RSB2 IO95RSB2 IO94RSB2 IO93RSB2 VCC IO92RSB2 IO91RSB2 IO90RSB2
176-Pin VQFP Pin Number 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 AGLP060 Function IO89RSB2 IO88RSB2 IO87RSB2 IO86RSB2 IO85RSB2 IO84RSB2 GND VCCIB2 IO83RSB2 IO82RSB2 GDC2/IO80RSB2 IO81RSB2 GDA2/IO78RSB2 GDB2/IO79RSB2 NC NC TCK TDI TMS VPUMP TDO TRST VJTAG GDA1/IO76RSB1 GDC0/IO73RSB1 GDB1/IO74RSB1 GDC1/IO72RSB1 VCCIB1 GND IO70RSB1 IO69RSB1 IO67RSB1 IO66RSB1 IO65RSB1 IO63RSB1
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Package Pin Assignments
176-Pin VQFP Pin Number 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 AGLP060 Function IO62RSB1 IO61RSB1 GCC2/IO60RSB1 GCB2/IO59RSB1 GCA2/IO58RSB1 GCA0/IO57RSB1 GCA1/IO56RSB1 VCCIB1 GND GCB0/IO55RSB1 GCB1/IO54RSB1 GCC0/IO53RSB1 GCC1/IO52RSB1 IO51RSB1 IO50RSB1 VCC IO48RSB1 IO47RSB1 IO45RSB1 IO44RSB1 IO43RSB1 VCCIB1 GND GBC2/IO40RSB1 IO39RSB1 GBB2/IO38RSB1 IO37RSB1 GBA2/IO36RSB1 GBA1/IO35RSB0 NC GBA0/IO34RSB0 NC GBB1/IO33RSB0 NC GBC1/IO31RSB0
176-Pin VQFP Pin Number 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 AGLP060 Function GBB0/IO32RSB0 GBC0/IO30RSB0 IO29RSB0 IO28RSB0 IO27RSB0 VCCIB0 GND IO26RSB0 IO25RSB0 IO24RSB0 IO23RSB0 IO22RSB0 IO21RSB0 IO20RSB0 IO19RSB0 IO18RSB0 VCC IO17RSB0 IO16RSB0 IO15RSB0 IO14RSB0 IO13RSB0 IO12RSB0 IO11RSB0 IO10RSB0 IO09RSB0 VCCIB0 GND IO07RSB0 IO08RSB0 GAC1/IO05RSB0 IO06RSB0 GAB1/IO03RSB0 GAC0/IO04RSB0 GAB0/IO02RSB0
176-Pin VQFP Pin Number 175 176 AGLP060 Function GAA1/IO01RSB0 GAA0/IO00RSB0
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IGLOO PLUS Low Power Flash FPGAs
201-Pin CSP
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx.
R ev i si o n 1 1
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Package Pin Assignments
201-Pin CSP Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 C1 C2 C3 C4 C5 AGLP030 Function NC IO04RSB0 IO06RSB0 IO09RSB0 IO11RSB0 IO13RSB0 IO17RSB0 IO18RSB0 IO24RSB0 IO26RSB0 IO27RSB0 IO31RSB0 NC NC NC NC NC IO08RSB0 IO05RSB0 IO07RSB0 IO15RSB0 IO14RSB0 IO16RSB0 IO20RSB0 IO22RSB0 IO34RSB0 IO29RSB0 NC NC NC NC NC GND IO00RSB0 IO02RSB0
201-Pin CSP Pin Number C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 E1 E2 E3 E4 E12 E13 E14 E15 F1 F2 AGLP030 Function IO12RSB0 IO23RSB0 IO19RSB0 IO28RSB0 IO32RSB0 IO35RSB0 NC GND IO41RSB1 IO37RSB1 IO117RSB3 IO118RSB3 NC GND IO01RSB0 IO03RSB0 IO10RSB0 IO21RSB0 IO25RSB0 IO30RSB0 IO33RSB0 GND NC IO36RSB1 IO39RSB1 IO115RSB3 IO114RSB3 NC NC NC NC GDC0/IO46RSB1 GDB0/IO48RSB1 IO113RSB3 IO116RSB3
201-Pin CSP Pin Number F3 F4 F6 F7 F8 F9 F10 F12 F13 F14 F15 G1 G2 G3 G4 G6 G7 G8 G9 G10 G12 G13 G14 G15 H1 H2 H3 H4 H6 H7 H8 H9 H10 H12 H13 AGLP030 Function IO119RSB3 IO111RSB3 GND VCC VCCIB0 VCCIB0 VCCIB0 NC NC IO40RSB1 IO38RSB1 NC IO112RSB3 IO110RSB3 IO109RSB3 VCCIB3 GND VCC GND GND NC NC IO42RSB1 IO44RSB1 NC GEB0/IO106RSB3 GEC0/IO108RSB3 NC VCCIB3 GND VCC GND VCCIB1 IO54RSB1 GDA0/IO47RSB1
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IGLOO PLUS Low Power Flash FPGAs
201-Pin CSP Pin Number H14 H15 J1 J2 J3 J4 J6 J7 J8 J9 J10 J12 J13 J14 J15 K1 K2 K3 K4 K6 K7 K8 K9 K10 K12 K13 K14 K15 L1 L2 L3 L4 L12 L13 L14 AGLP030 Function IO45RSB1 IO43RSB1 GEA0/IO107RSB3 IO105RSB3 IO104RSB3 IO102RSB3 VCCIB3 GND VCC GND VCCIB1 NC NC IO52RSB1 IO50RSB1 IO103RSB3 IO101RSB3 IO99RSB3 IO100RSB3 GND VCCIB2 VCCIB2 VCCIB2 VCCIB1 NC IO57RSB1 IO49RSB1 IO53RSB1 IO96RSB3 IO98RSB3 IO95RSB3 IO94RSB3 NC NC IO51RSB1
201-Pin CSP Pin Number L15 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 P1 P2 P3 P4 AGLP030 Function IO58RSB1 IO93RSB3 IO92RSB3 IO97RSB3 GND NC IO79RSB2 IO77RSB2 IO72RSB2 IO70RSB2 IO61RSB2 IO59RSB2 GND NC IO55RSB1 IO56RSB1 NC NC GND NC IO88RSB2 IO81RSB2 IO75RSB2 IO68RSB2 IO66RSB2 IO65RSB2 IO71RSB2 IO63RSB2 GND TDO VJTAG NC NC NC NC
201-Pin CSP Pin Number P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 AGLP030 Function IO87RSB2 IO86RSB2 IO84RSB2 IO80RSB2 IO74RSB2 IO73RSB2 IO76RSB2 IO67RSB2 IO64RSB2 VPUMP TRST NC NC IO91RSB2 FF/IO90RSB2 IO89RSB2 IO83RSB2 IO82RSB2 IO85RSB2 IO78RSB2 IO69RSB2 IO62RSB2 IO60RSB2 TMS TDI TCK
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Package Pin Assignments
201-Pin CSP Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 C1 C2 C3 C4 C5 AGLP060 Function IO150RSB3 GAA0/IO00RSB0 GAC0/IO04RSB0 IO08RSB0 IO11RSB0 IO15RSB0 IO17RSB0 IO18RSB0 IO22RSB0 IO26RSB0 IO29RSB0 GBC1/IO31RSB0 GBA2/IO36RSB1 IO41RSB1 NC IO151RSB3 GAB2/IO154RSB3 IO06RSB0 IO09RSB0 IO13RSB0 IO10RSB0 IO12RSB0 IO20RSB0 IO23RSB0 IO25RSB0 IO24RSB0 IO27RSB0 IO37RSB1 IO46RSB1 IO42RSB1 IO155RSB3 GAA2/IO156RSB3 GND GAA1/IO01RSB0 GAB1/IO03RSB0
201-Pin CSP Pin Number C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 E1 E2 E3 E4 E12 E13 E14 E15 F1 F2 AGLP060 Function IO07RSB0 IO16RSB0 IO21RSB0 IO28RSB0 GBB1/IO33RSB0 GBA1/IO35RSB0 GBB2/IO38RSB1 GND IO48RSB1 IO39RSB1 IO146RSB3 IO144RSB3 IO148RSB3 GND GAB0/IO02RSB0 GAC1/IO05RSB0 IO14RSB0 IO19RSB0 GBC0/IO30RSB0 GBB0/IO32RSB0 GBA0/IO34RSB0 GND GBC2/IO40RSB1 IO51RSB1 IO44RSB1 IO142RSB3 IO149RSB3 IO153RSB3 GAC2/IO152RSB3 IO43RSB1 IO49RSB1 GCC0/IO53RSB1 GCB0/IO55RSB1 IO141RSB3 GFC1/IO140RSB3
201-Pin CSP Pin Number F3 F4 F6 F7 F8 F9 F10 F12 F13 F14 F15 G1* G2 G3 G4 G6 G7 G8 G9 G10 G12 G13 G14 G15 H1* H2 H3 H4 H6 H7 H8 H9 H10 H12 H13 AGLP060 Function IO145RSB3 IO147RSB3 GND VCC VCCIB0 VCCIB0 VCCIB0 IO47RSB1 IO45RSB1 GCC1/IO52RSB1 GCA1/IO56RSB1 VCOMPLF GFB0/IO137RSB3 GFC0/IO139RSB3 IO143RSB3 VCCIB3 GND VCC GND GND IO50RSB1 GCB1/IO54RSB1 GCC2/IO60RSB1 GCA2/IO58RSB1 VCCPLF GFA1/IO136RSB3 GFB1/IO138RSB3 NC VCCIB3 GND VCC GND VCCIB1 GCB2/IO59RSB1 GCA0/IO57RSB1
* Pin numbers G1 and H1 must be connected to ground because a PLL is not supported for AGLP060-CS/G201.
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IGLOO PLUS Low Power Flash FPGAs
201-Pin CSP Pin Number H14 H15 J1 J2 J3 J4 J6 J7 J8 J9 J10 J12 J13 J14 J15 K1 K2 K3 K4 K6 K7 K8 K9 K10 K12 K13 K14 K15 L1 L2 L3 L4 L12 L13 L14 AGLP060 Function IO64RSB1 IO62RSB1 GFA2/IO134RSB3 GFA0/IO135RSB3 GFB2/IO133RSB3 IO131RSB3 VCCIB3 GND VCC GND VCCIB1 IO61RSB1 IO63RSB1 IO68RSB1 IO66RSB1 IO130RSB3 GFC2/IO132RSB3 IO127RSB3 IO129RSB3 GND VCCIB2 VCCIB2 VCCIB2 VCCIB1 IO65RSB1 IO67RSB1 IO69RSB1 IO70RSB1 IO126RSB3 IO128RSB3 IO121RSB3 IO123RSB3 GDB1/IO74RSB1 GDC1/IO72RSB1 IO71RSB1
201-Pin CSP Pin Number L15 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 P1 P2 P3 P4 AGLP060 Function GDC0/IO73RSB1 IO122RSB3 IO124RSB3 IO119RSB3 GND IO125RSB3 IO98RSB2 IO96RSB2 IO91RSB2 IO89RSB2 IO82RSB2 GDA2/IO78RSB2 GND GDA1/IO76RSB1 GDA0/IO77RSB1 GDB0/IO75RSB1 IO117RSB3 IO120RSB3 GND GEB1/IO114RSB3 IO107RSB2 IO100RSB2 IO94RSB2 IO87RSB2 IO85RSB2 GDC2/IO80RSB2 IO90RSB2 IO84RSB2 GND TDO VJTAG GEC0/IO115RSB3 GEC1/IO116RSB3 GEA0/IO111RSB3 GEA1/IO112RSB3 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
201-Pin CSP Pin Number P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 R1 R2 R3 R4 AGLP060 Function IO106RSB2 IO105RSB2 IO103RSB2 IO99RSB2 IO93RSB2 IO92RSB2 IO95RSB2 IO86RSB2 IO83RSB2 VPUMP TRST IO118RSB3 GEB0/IO113RSB3 GEA2/IO110RSB2 FF/GEB2/IO109RS B2 GEC2/IO108RSB2 IO102RSB2 IO101RSB2 IO104RSB2 IO97RSB2 IO88RSB2 IO81RSB2 GDB2/IO79RSB2 TMS TDI TCK
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Package Pin Assignments
281-Pin CSP
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx
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IGLOO PLUS Low Power Flash FPGAs
281-Pin CSP Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 AGLP125 Function GND GAB0/IO02RSB0 GAC1/IO05RSB0 IO09RSB0 IO13RSB0 IO15RSB0 IO18RSB0 IO23RSB0 IO25RSB0 VCCIB0 IO33RSB0 IO41RSB0 IO43RSB0 IO46RSB0 IO55RSB0 IO56RSB0 GBC1/IO58RSB0 GBA0/IO61RSB0 GND GAA2/IO211RSB3 VCCIB0 GAB1/IO03RSB0 GAC0/IO04RSB0 IO11RSB0 GND IO21RSB0 IO22RSB0 IO28RSB0 IO32RSB0 IO36RSB0 IO39RSB0 IO42RSB0 GND IO52RSB0 GBC0/IO57RSB0 GBA1/IO62RSB0
281-Pin CSP Pin Number B18 B19 C1 C2 C6 C14 C18 C19 D1 D2 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D18 D19 E1 E2 E4 E5 E6 E7 E8 E9 E10 E11 E12 AGLP125 Function VCCIB1 IO64RSB1 GAB2/IO209RSB3 IO210RSB3 IO12RSB0 IO47RSB0 IO54RSB0 GBB2/IO65RSB1 IO206RSB3 IO208RSB3 GAA0/IO00RSB0 GAA1/IO01RSB0 IO10RSB0 IO17RSB0 IO24RSB0 IO27RSB0 GND IO31RSB0 IO40RSB0 IO49RSB0 IO45RSB0 GBB0/IO59RSB0 GBA2/IO63RSB1 GBC2/IO67RSB1 IO66RSB1 IO203RSB3 IO205RSB3 IO07RSB0 IO06RSB0 IO14RSB0 IO20RSB0 IO29RSB0 IO34RSB0 IO30RSB0 IO37RSB0 IO38RSB0
281-Pin CSP Pin Number E13 E14 E15 E16 E18 E19 F1 F2 F3 F4 F5 F15 F16 F17 F18 F19 G1 G2 G4 G5 G7 G8 G9 G10 G11 G12 G13 G15 G16 G18 G19 H1 H2 H4 H5 H7 AGLP125 Function IO48RSB0 GBB1/IO60RSB0 IO53RSB0 IO69RSB1 IO68RSB1 IO71RSB1 IO198RSB3 GND IO201RSB3 IO204RSB3 IO16RSB0 IO50RSB0 IO74RSB1 IO72RSB1 GND IO73RSB1 IO195RSB3 IO200RSB3 IO202RSB3 IO08RSB0 GAC2/IO207RSB3 VCCIB0 IO26RSB0 IO35RSB0 IO44RSB0 VCCIB0 IO51RSB0 IO70RSB1 IO75RSB1 GCC0/IO80RSB1 GCB1/IO81RSB1 GFB0/IO191RSB3 IO196RSB3 GFC1/IO194RSB3 GFB1/IO192RSB3 VCCIB3
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Package Pin Assignments
281-Pin CSP Pin Number H8 H9 H10 H11 H12 H13 H15 H16 H18 H19 J1 J2 J4 J5 J7 J8 J9 J10 J11 J12 J13 J15 J16 J18 J19 K1 K2 K4 K5 K7 K8 K9 K10 K11 K12 K13 AGLP125 Function VCC VCCIB0 VCC VCCIB0 VCC VCCIB1 IO77RSB1 GCB0/IO82RSB1 GCA1/IO83RSB1 GCA2/IO85RSB1 VCOMPLF GFA0/IO189RSB3 VCCPLF GFC0/IO193RSB3 GFA2/IO188RSB3 VCCIB3 GND GND GND VCCIB1 GCC1/IO79RSB1 GCA0/IO84RSB1 GCB2/IO86RSB1 IO76RSB1 IO78RSB1 VCCIB3 GFA1/IO190RSB3 GND IO19RSB0 IO197RSB3 VCC GND GND GND VCC GCC2/IO87RSB1
281-Pin CSP Pin Number K15 K16 K18 K19 L1 L2 L4 L5 L7 L8 L9 L10 L11 L12 L13 L15 L16 L18 L19 M1 M2 M4 M5 M7 M8 M9 M10 M11 M12 M13 M15 M16 M18 M19 N1 N2 AGLP125 Function IO89RSB1 GND IO88RSB1 VCCIB1 GFB2/IO187RSB3 IO185RSB3 GFC2/IO186RSB3 IO184RSB3 IO199RSB3 VCCIB3 GND GND GND VCCIB1 IO95RSB1 IO91RSB1 NC IO90RSB1 NC IO180RSB3 IO179RSB3 IO181RSB3 IO183RSB3 VCCIB3 VCC VCCIB2 VCC VCCIB2 VCC VCCIB1 IO122RSB2 IO93RSB1 IO92RSB1 NC IO178RSB3 IO175RSB3
281-Pin CSP Pin Number N4 N5 N7 N8 N9 N10 N11 N12 N13 N15 N16 N18 N19 P1 P2 P3 P4 P5 P15 P16 P17 P18 P19 R1 R2 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 AGLP125 Function IO182RSB3 IO161RSB2 GEA2/IO164RSB2 VCCIB2 IO137RSB2 IO135RSB2 IO131RSB2 VCCIB2 VPUMP IO117RSB2 IO96RSB1 IO98RSB1 IO94RSB1 IO174RSB3 GND IO176RSB3 IO177RSB3 GEA0/IO165RSB3 IO111RSB2 IO108RSB2 GDC1/IO99RSB1 GND IO97RSB1 IO173RSB3 IO172RSB3 GEC1/IO170RSB3 GEB1/IO168RSB3 IO154RSB2 IO149RSB2 IO146RSB2 IO138RSB2 IO134RSB2 IO132RSB2 IO130RSB2 IO118RSB2 IO112RSB2
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IGLOO PLUS Low Power Flash FPGAs
281-Pin CSP Pin Number R15 R16 R18 R19 T1 T2 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T18 T19 U1 U2 U6 U14 U18 U19 V1 V2 V3 V4 V5 V6 V7 V8 V9 AGLP125 Function IO109RSB2 GDA1/IO103RSB1 GDB0/IO102RSB1 GDC0/IO100RSB1 IO171RSB3 GEC0/IO169RSB3 GEB0/IO167RSB3 IO157RSB2 IO158RSB2 IO148RSB2 IO145RSB2 IO143RSB2 GND IO129RSB2 IO126RSB2 IO125RSB2 IO116RSB2 GDC2/IO107RSB2 TMS VJTAG GDB1/IO101RSB1 IO160RSB2 GEA1/IO166RSB3 IO151RSB2 IO121RSB2 TRST GDA0/IO104RSB1 IO159RSB2 VCCIB3 GEC2/IO162RSB2 IO156RSB2 IO153RSB2 GND IO144RSB2 IO141RSB2 IO140RSB2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19
281-Pin CSP Pin Number V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W1 W2 AGLP125 Function IO133RSB2 IO127RSB2 IO123RSB2 IO120RSB2 GND IO113RSB2 GDA2/IO105RSB2 TDI VCCIB2 TDO GND FF/GEB2/IO163RSB 2 IO155RSB2 IO152RSB2 IO150RSB2 IO147RSB2 IO142RSB2 IO139RSB2 IO136RSB2 VCCIB2 IO128RSB2 IO124RSB2 IO119RSB2 IO115RSB2 IO114RSB2 IO110RSB2 GDB2/IO106RSB2 TCK GND
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Package Pin Assignments
289-Pin CSP
A1 Ball Pad Corner
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U
Note: This is the bottom view of the package.
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx .
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IGLOO PLUS Low Power Flash FPGAs
289-Pin CSP Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 AGLP030 Function IO03RSB0 NC NC GND IO10RSB0 IO14RSB0 IO16RSB0 IO18RSB0 GND IO23RSB0 IO27RSB0 NC NC GND NC NC IO30RSB0 IO01RSB0 GND NC NC IO07RSB0 NC VCCIB0 IO17RSB0 IO19RSB0 IO24RSB0 IO28RSB0 VCCIB0 NC NC NC IO31RSB0 GND NC IO00RSB0 IO04RSB0
289-Pin CSP Pin Number C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 E1 E2 E3 E4 E5 E6 AGLP030 Function NC VCCIB0 IO09RSB0 IO13RSB0 IO15RSB0 IO21RSB0 GND IO29RSB0 NC NC NC GND IO34RSB0 NC NC IO119RSB3 GND IO02RSB0 NC NC NC GND IO20RSB0 IO25RSB0 NC NC GND IO32RSB0 IO35RSB0 NC NC VCCIB3 IO114RSB3 IO115RSB3 IO118RSB3 IO05RSB0 NC
289-Pin CSP Pin Number E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 G1 G2 G3 G4 G5 G6 G7 G8 G9 AGLP030 Function IO06RSB0 IO11RSB0 IO22RSB0 IO26RSB0 VCCIB0 NC IO33RSB0 IO36RSB1 IO38RSB1 VCCIB1 NC IO111RSB3 NC IO116RSB3 VCCIB3 IO117RSB3 NC NC IO08RSB0 IO12RSB0 NC NC NC NC GND NC IO37RSB1 IO41RSB1 IO110RSB3 GND IO113RSB3 NC NC NC GND GND VCC
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Package Pin Assignments
289-Pin CSP Pin Number G10 G11 G12 G13 G14 G15 G16 G17 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 AGLP030 Function GND GND IO40RSB1 NC IO39RSB1 IO44RSB1 NC GND NC GEC0/IO108RSB3 NC IO112RSB3 NC IO109RSB3 GND GND GND GND GND NC NC IO45RSB1 VCCIB1 GDB0/IO48RSB1 IO42RSB1 NC GEA0/IO107RSB3 VCCIB3 IO105RSB3 NC NC VCC GND GND GND VCC IO50RSB1
289-Pin CSP Pin Number J13 J14 J15 J16 J17 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 AGLP030 Function IO43RSB1 IO51RSB1 IO52RSB1 GDC0/IO46RSB1 GDA0/IO47RSB1 GND GEB0/IO106RSB3 IO102RSB3 IO104RSB3 IO99RSB3 NC GND GND GND GND GND NC NC NC IO53RSB1 GND IO49RSB1 IO103RSB3 IO101RSB3 NC GND NC NC GND GND VCC GND GND IO58RSB1 IO54RSB1 VCCIB1 NC
289-Pin CSP Pin Number L16 L17 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 P1 AGLP030 Function NC NC NC VCCIB3 IO100RSB3 IO98RSB3 IO93RSB3 IO97RSB3 NC NC IO71RSB2 NC IO63RSB2 NC IO57RSB1 NC NC NC VCCIB1 NC NC IO95RSB3 IO96RSB3 GND NC IO85RSB2 IO79RSB2 IO77RSB2 VCCIB2 NC NC IO59RSB2 NC GND IO56RSB1 IO55RSB1 IO94RSB3
3- 18
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IGLOO PLUS Low Power Flash FPGAs
289-Pin CSP Pin Number P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 AGLP030 Function NC GND NC NC IO87RSB2 IO80RSB2 GND IO72RSB2 IO67RSB2 IO61RSB2 NC VCCIB2 NC IO60RSB2 IO62RSB2 VJTAG GND IO91RSB2 NC NC NC VCCIB2 IO83RSB2 IO78RSB2 IO74RSB2 IO70RSB2 GND NC NC NC NC TMS TRST IO92RSB3 IO89RSB2 NC GND
289-Pin CSP Pin Number T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 AGLP030 Function NC IO84RSB2 IO81RSB2 IO76RSB2 VCCIB2 IO69RSB2 IO65RSB2 IO64RSB2 NC GND NC TDI TDO FF/IO90RSB2 GND NC IO88RSB2 IO86RSB2 IO82RSB2 GND IO75RSB2 IO73RSB2 IO68RSB2 IO66RSB2 GND NC NC NC TCK VPUMP
R ev i si o n 1 1
3- 19
Package Pin Assignments
289-Pin CSP Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 AGLP060 Function GAB1/IO03RSB0 NC NC GND IO10RSB0 IO14RSB0 IO16RSB0 IO18RSB0 GND IO23RSB0 IO27RSB0 NC NC GND NC NC GBC0/IO30RSB0 GAA1/IO01RSB0 GND NC NC IO07RSB0 NC VCCIB0 IO17RSB0 IO19RSB0 IO24RSB0 IO28RSB0 VCCIB0 NC NC NC GBC1/IO31RSB0 GND IO155RSB3 GAA0/IO00RSB0 GAC0/IO04RSB0 NC
289-Pin CSP Pin Number C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 E1 E2 E3 E4 E5 E6 E7 E8 AGLP060 Function VCCIB0 IO09RSB0 IO13RSB0 IO15RSB0 IO21RSB0 GND IO29RSB0 NC NC NC GND GBA0/IO34RSB0 IO39RSB1 IO150RSB3 IO151RSB3 GND GAB0/IO02RSB0 NC NC NC GND IO20RSB0 IO25RSB0 NC NC GND GBB0/IO32RSB0 GBA1/IO35RSB0 IO37RSB1 IO42RSB1 VCCIB3 IO147RSB3 GAC2/IO152RSB3 GAA2/IO156RSB3 GAC1/IO05RSB0 NC IO06RSB0 IO11RSB0
289-Pin CSP Pin Number E9 E10 E11 E12 E13 E14 E15 E16 E17 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 AGLP060 Function IO22RSB0 IO26RSB0 VCCIB0 NC GBB1/IO33RSB0 GBA2/IO36RSB1 GBB2/IO38RSB1 VCCIB1 IO44RSB1 GFC1/IO140RSB3 IO142RSB3 IO149RSB3 VCCIB3 GAB2/IO154RSB3 IO153RSB3 NC IO08RSB0 IO12RSB0 NC NC NC GBC2/IO40RSB1 GND IO43RSB1 IO46RSB1 IO45RSB1 GFC0/IO139RSB3 GND IO144RSB3 IO145RSB3 IO146RSB3 IO148RSB3 GND GND VCC GND GND IO48RSB1
3- 20
R ev i sio n 1 1
IGLOO PLUS Low Power Flash FPGAs
289-Pin CSP Pin Number G13 G14 G15 G16 G17 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 AGLP060 Function IO41RSB1 IO47RSB1 IO49RSB1 IO50RSB1 GND VCOMPLF GFB0/IO137RSB3 NC IO141RSB3 IO143RSB3 GFB1/IO138RSB3 GND GND GND GND GND GCC1/IO52RSB1 IO51RSB1 GCA0/IO57RSB1 VCCIB1 GCA2/IO58RSB1 GCC0/IO53RSB1 VCCPLF GFA1/IO136RSB3 VCCIB3 IO131RSB3 IO130RSB3 IO129RSB3 VCC GND GND GND VCC GCB2/IO59RSB1 GCB1/IO54RSB1 IO62RSB1 IO63RSB1 GCB0/IO55RSB1
289-Pin CSP Pin Number J17 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 M1 M2 M3 AGLP060 Function GCA1/IO56RSB1 GND GFA0/IO135RSB3 GFB2/IO133RSB3 IO128RSB3 IO123RSB3 IO125RSB3 GND GND GND GND GND IO64RSB1 IO61RSB1 IO66RSB1 IO65RSB1 GND GCC2/IO60RSB1 GFA2/IO134RSB3 GFC2/IO132RSB3 IO127RSB3 GND IO121RSB3 GEC1/IO116RSB3 GND GND VCC GND GND GDC1/IO72RSB1 GDB1/IO74RSB1 VCCIB1 IO70RSB1 IO68RSB1 IO67RSB1 IO126RSB3 VCCIB3 IO124RSB3
289-Pin CSP Pin Number M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 AGLP060 Function IO122RSB3 GEB0/IO113RSB3 GEB1/IO114RSB3 NC NC IO90RSB2 NC IO83RSB2 NC GDA1/IO76RSB1 GDA0/IO77RSB1 IO71RSB1 IO69RSB1 VCCIB1 IO119RSB3 IO120RSB3 GEC0/IO115RSB3 GEA0/IO111RSB3 GND NC IO104RSB2 IO98RSB2 IO96RSB2 VCCIB2 NC NC GDB2/IO79RSB2 NC GND GDB0/IO75RSB1 GDC0/IO73RSB1 IO118RSB3 IO117RSB3 GND NC NC IO106RSB2 IO99RSB2
R ev i si o n 1 1
3- 21
Package Pin Assignments
289-Pin CSP Pin Number P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 AGLP060 Function GND IO91RSB2 IO86RSB2 IO81RSB2 NC VCCIB2 NC GDA2/IO78RSB2 GDC2/IO80RSB2 VJTAG GND GEA2/IO110RSB2 NC NC NC VCCIB2 IO102RSB2 IO97RSB2 IO93RSB2 IO89RSB2 GND NC NC NC NC TMS TRST GEA1/IO112RSB3 GEC2/IO108RSB2 NC GND NC IO103RSB2 IO100RSB2 IO95RSB2 VCCIB2 IO88RSB2 IO84RSB2 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17
289-Pin CSP Pin Number T12 T13 T14 T15 T16 T17 U1 AGLP060 Function IO82RSB2 NC GND NC TDI TDO FF/GEB2/IO109RS B2 GND NC IO107RSB2 IO105RSB2 IO101RSB2 GND IO94RSB2 IO92RSB2 IO87RSB2 IO85RSB2 GND NC NC NC TCK VPUMP
3- 22
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IGLOO PLUS Low Power Flash FPGAs
289-Pin CSP Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 AGLP125 Function GAB1/IO03RSB0 IO11RSB0 IO08RSB0 GND IO19RSB0 IO24RSB0 IO26RSB0 IO30RSB0 GND IO35RSB0 IO38RSB0 IO40RSB0 IO42RSB0 GND IO48RSB0 IO54RSB0 GBC0/IO57RSB0 GAA1/IO01RSB0 GND IO06RSB0 IO13RSB0 IO15RSB0 IO21RSB0 VCCIB0 IO28RSB0 IO31RSB0 IO37RSB0 IO39RSB0 VCCIB0 IO44RSB0 IO46RSB0 IO49RSB0 GBC1/IO58RSB0 GND IO210RSB3 GAA0/IO00RSB0 GAC0/IO04RSB0 IO09RSB0
289-Pin CSP Pin Number C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 E1 E2 E3 E4 E5 E6 E7 E8 AGLP125 Function VCCIB0 IO17RSB0 IO23RSB0 IO27RSB0 IO33RSB0 GND IO43RSB0 IO45RSB0 IO50RSB0 IO52RSB0 GND GBA0/IO61RSB0 IO68RSB1 IO204RSB3 IO205RSB3 GND GAB0/IO02RSB0 IO07RSB0 IO10RSB0 IO18RSB0 GND IO34RSB0 IO41RSB0 IO47RSB0 IO55RSB0 GND GBB0/IO59RSB0 GBA1/IO62RSB0 IO66RSB1 IO70RSB1 VCCIB3 IO200RSB3 GAC2/IO207RSB3 GAA2/IO211RSB3 GAC1/IO05RSB0 IO12RSB0 IO16RSB0 IO22RSB0
289-Pin CSP Pin Number E9 E10 E11 E12 E13 E14 E15 E16 E17 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 AGLP125 Function IO32RSB0 IO36RSB0 VCCIB0 IO56RSB0 GBB1/IO60RSB0 GBA2/IO63RSB1 GBB2/IO65RSB1 VCCIB1 IO73RSB1 GFC1/IO194RSB3 IO196RSB3 IO202RSB3 VCCIB3 GAB2/IO209RSB3 IO208RSB3 IO14RSB0 IO20RSB0 IO25RSB0 IO29RSB0 IO51RSB0 IO53RSB0 GBC2/IO67RSB1 GND IO75RSB1 IO71RSB1 IO77RSB1 GFC0/IO193RSB3 GND IO198RSB3 IO203RSB3 IO201RSB3 IO206RSB3 GND GND VCC GND GND IO72RSB1
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Package Pin Assignments
289-Pin CSP Pin Number G13 G14 G15 G16 G17 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 AGLP125 Function IO64RSB1 IO69RSB1 IO78RSB1 IO76RSB1 GND VCOMPLF GFB0/IO191RSB3 IO195RSB3 IO197RSB3 IO199RSB3 GFB1/IO192RSB3 GND GND GND GND GND GCC1/IO79RSB1 IO74RSB1 GCA0/IO84RSB1 VCCIB1 GCA2/IO85RSB1 GCC0/IO80RSB1 VCCPLF GFA1/IO190RSB3 VCCIB3 IO185RSB3 IO183RSB3 IO181RSB3 VCC GND GND GND VCC GCB2/IO86RSB1 GCB1/IO81RSB1 IO90RSB1 IO89RSB1 GCB0/IO82RSB1
289-Pin CSP Pin Number J17 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 M1 M2 M3 AGLP125 Function GCA1/IO83RSB1 GND GFA0/IO189RSB3 GFB2/IO187RSB3 IO179RSB3 IO175RSB3 IO177RSB3 GND GND GND GND GND IO88RSB1 IO94RSB1 IO95RSB1 IO93RSB1 GND GCC2/IO87RSB1 GFA2/IO188RSB3 GFC2/IO186RSB3 IO182RSB3 GND IO173RSB3 GEC1/IO170RSB3 GND GND VCC GND GND GDC1/IO99RSB1 GDB1/IO101RSB1 VCCIB1 IO98RSB1 IO92RSB1 IO91RSB1 IO184RSB3 VCCIB3 IO176RSB3
289-Pin CSP Pin Number M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 AGLP125 Function IO172RSB3 GEB0/IO167RSB3 GEB1/IO168RSB3 IO159RSB2 IO161RSB2 IO135RSB2 IO128RSB2 IO121RSB2 IO113RSB2 GDA1/IO103RSB1 GDA0/IO104RSB1 IO97RSB1 IO96RSB1 VCCIB1 IO180RSB3 IO178RSB3 GEC0/IO169RSB3 GEA0/IO165RSB3 GND IO156RSB2 IO148RSB2 IO144RSB2 IO137RSB2 VCCIB2 IO119RSB2 IO111RSB2 GDB2/IO106RSB2 IO109RSB2 GND GDB0/IO102RSB1 GDC0/IO100RSB1 IO174RSB3 IO171RSB3 GND IO160RSB2 IO157RSB2 IO154RSB2 IO152RSB2
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IGLOO PLUS Low Power Flash FPGAs
289-Pin CSP Pin Number P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 AGLP125 Function GND IO132RSB2 IO125RSB2 IO126RSB2 IO112RSB2 VCCIB2 IO108RSB2 GDA2/IO105RSB2 GDC2/IO107RSB2 VJTAG GND GEA2/IO164RSB2 IO158RSB2 IO155RSB2 IO150RSB2 VCCIB2 IO145RSB2 IO141RSB2 IO134RSB2 IO130RSB2 GND IO118RSB2 IO116RSB2 IO114RSB2 IO110RSB2 TMS TRST GEA1/IO166RSB3 GEC2/IO162RSB2 IO153RSB2 GND IO147RSB2 IO143RSB2 IO140RSB2 IO139RSB2 VCCIB2 IO131RSB2 IO127RSB2 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17
289-Pin CSP Pin Number T12 T13 T14 T15 T16 T17 U1 AGLP125 Function IO124RSB2 IO122RSB2 GND IO115RSB2 TDI TDO FF/GEB2/IO163RS B2 GND IO151RSB2 IO149RSB2 IO146RSB2 IO142RSB2 GND IO138RSB2 IO136RSB2 IO133RSB2 IO129RSB2 GND IO123RSB2 IO120RSB2 IO117RSB2 TCK VPUMP
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3- 25
4 - Datasheet Information
List of Changes
The following table lists critical changes that were made in each revision of the IGLOO PLUS datasheet. Revision Revision 11 (Jun 2009) Changes The versioning system for datasheets has been changed. Datasheets are assigned a revision number that increments each time the datasheet is revised. The "IGLOO PLUS Device Status" table indicates the status for each device in the family. The "Reprogrammable Flash Technology" section was revised to add "250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance." The "I/Os with Advanced I/O Standards" section was revised to add definitions for hot-swap and cold-sparing. Conditional statements regarding hot insertion were removed from the description of VI in Table 2-1 * Absolute Maximum Ratings, since all IGLOO PLUS devices are hot insertion enabled. Table 2-2 * Recommended Operating Conditions1,2 was revised. 1.2 V DC wide range supply voltage and 3.3 V wide range supply voltage (SAR 26270) were added for VCCI. VJTAG DC Voltage was revised (SAR 24052). The value range for VPUMP programming voltage for operation was changed from "0 to 3.45" to "0 to 3.6" (SAR 25220). Page N/A
I 1-7 2-1
2-2
Table 2-6 * Temperature and Voltage Derating Factors for Timing Delays 2-6, 2-7 (normalized to TJ = 70C, VCC = 1.425 V) and Table 2-7 * Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70C, VCC = 1.14 V) were revised. Table 2-8 * Power Supply State per Mode is new. The tables in the "Quiescent Supply Current" section were updated (SARs 24882 and 24112). Some of the table notes were changed or deleted. VIH maximum values in tables were updated as needed to 3.6 V (SAR 20990 2-7 2-7 N/A
and SAR 79370).
R ev i si o n 1 1
4 -1
Datasheet Information
Revision
Changes
Page
Revision 11 (continued) The values in the following tables were updated. 3.3 V LVCMOS and 1.2 V LVCMOS wide range were added to the tables where applicable. Table 2-13 * Summary of I/O Input Buffer Power (per pin) - Default I/O Software Settings Table 2-14 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings1 Table 2-21 * Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions--Software Default Settings Table 2-22 * Summary of Maximum and Minimum DC Input Levels Table 2-23 * Summary of AC Measuring Points Table 2-25 * Summary of I/O Timing Characteristics--Software Default Settings, STD Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Table 2-26 * Summary of I/O Timing Characteristics--Software Default Settings, STD Speed Grade Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Table 2-28 * I/O Output Buffer Maximum Resistances 1 A table note was added to Table 2-16 * Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices and Table 2-18 * Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices stating the value for PDC4 is the minimum contribution of the PLL when operating at lowest frequency. Table 2-29 * I/O Weak Pull-Up/Pull-Down Resistances was revised, including addition of 3.3 V and 1.2 V LVCMOS wide range. The notes defining RWEAK PULLUP-MAX and RWEAK PULLDOWN-MAX were revised (SAR 21348). Table 2-30 * I/O Short Currents IOSH/IOSL was revised to include data for 3.3 V and 1.2 V LVCMOS wide range (SAR 79353 and SAR 79366). Table 2-31 * Duration of Short Circuit Event before Failure was revised to change the maximum temperature from 110C to 100C, with an example of six months instead of three months (SAR 26259). The tables in the "Single-Ended I/O Characteristics" section were updated. Notes clarifying IIL and IIH were added. Tables for 3.3 V LVCMOS and 1.2 V LVCMOS wide range were added (SAR 79370, SAR 79353, and SAR 79366). Notes in the wide range tables state that the minimum drive strength for any LVCMOS 3.3 V (or LVCMOS 1.2 V) software configuration when run in wide range is 100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models (SAR 25700). The following sentence was deleted from the "2.5 V LVCMOS" section: It uses a 5 V-tolerant input buffer and push-pull output buffer (SAR 24916). 2-32 2-9 2-9 2-19 2-20 2-21
2-22
2-23 2-24 2-11, 2-12
2-25
2-25 2-26
2-27
The tables in the "Input Register" section, "Output Register" section, and "Output 2-45 Enable Register" section were updated. The tables in the "VersaTile through Characteristics" section were updated. 2-56
4- 2
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IGLOO PLUS Low Power Flash FPGAs
Revision
Changes
Page 2-58
Revision 11 (continued) The following tables were updated in the "Global Tree Timing Characteristics" section: Table 2-85 * AGLP060 Global Resource (1.5 V) Table 2-86 * AGLP125 Global Resource (1.5 V) Table 2-88 * AGLP060 Global Resource (1.2 V) Table 2-90 * IGLOO PLUS CCC/PLL Specification and Table 2-91 * IGLOO PLUS CCC/PLL Specification were revised (SAR 79388). VCO output jitter and maximum peak-to-peak jitter data were changed. Three notes were added to the table in connection with these changes. Figure 2-28 * Write Access after Write onto Same Address and Figure 2-29 * Write Access after Read onto Same Address were deleted. The tables in the "SRAM", "FIFO" and "Embedded FlashROM Characteristics" sections were updated. Revision 10 (Apr 2009) Product Brief v1.5 DC and Switching Characteristics Advance v0.5 Revision 9 (Feb 2009) Product Brief v1.4 The -F speed grade is no longer offered for IGLOO PLUS devices. References to it have been removed from the document. The speed grade column and note regarding -F speed grade were removed from "IGLOO PLUS Ordering Information". The "Speed Grade and Temperature Grade Matrix" section was removed. The "Advanced I/O" section was revised to add two bullets regarding support of wide range power supply voltage. The "I/Os with Advanced I/O Standards" section was revised to add 3.0 V wide range to the list of supported voltages. The "Wide Range I/O Support" section is new. Revision 8 (Jan 2009) Packaging v1.5 Revision 7 (Dec 2008) Product Brief v1.3 The "201-Pin CSP" pin table was revised to add a note regarding pins G1 and H1. A note was added to IGLOO PLUS Devices: "AGLP060 in CS201 does not support the PLL." Table 2 * IGLOO PLUS FPGAs Package Size Dimensions was updated to change the nominal size of VQ176 from 100 to 400 mm2. Revision 6 (Oct 2008) DC and Switching Characteristics Advance v0.4 Data was revised significantly in the following tables: Table 2-25 * Summary of I/O Timing Characteristics--Software Default Settings, STD Speed Grade, Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Table 2-26 * Summary of I/O Timing Characteristics--Software Default Settings, STD Speed Grade Commercial-Case Conditions: TJ = 70C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Table 2-50 * 2.5 LVCMOS Low Slew - Applies to 1.2 V DC Core Voltage Table 2-51 * 2.5 V LVCMOS High Slew - Applies to 1.2 V DC Core Voltage Revision 5 (Aug 2008) Product Brief v1.2 The VQ128 and VQ176 packages were added to Table 1 * IGLOO PLUS Product Family, the "I/Os Per Package 1" table, Table 2 * IGLOO PLUS FPGAs Package Size Dimensions, "IGLOO PLUS Ordering Information", and the "Temperature Grade Offerings" table. The "128-Pin VQFP" package drawing and pin table are new. The "176-Pin VQFP" package drawing and pin table are new.
2-61
N/A 2-68, 2-77 III, IV
I 1-7
3-8
I II 2-22, 2-33
I to IV
Packaging v1.4
3-2 3-5
R ev i si o n 1 1
4 -3
Datasheet Information
Revision Revision 4 (Jul 2008) Product Brief v1.1 DC and Switching Characteristics Advance v0.3 Revision 3 (Jun 2008) DC and Switching Characteristics Advance v0.2
Changes As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to 1.5 V.
Page N/A
Tables have been updated to reflect default values in the software. The default I/O capacitance is 5 pF. Tables have been updated to include the LVCMOS 1.2 V I/O set.
N/A
Table note 3 was updated in Table 2-2 * Recommended Operating Conditions1,2 to add the sentence, "VCCI should be at the same voltage within a given I/O bank." References to table notes 5, 6, 7, and 8 were added. Reference to table note 3 was removed from VPUMP Operation and placed next to VCC. Table 2-4 * Overshoot and Undershoot Limits 1 was revised to remove "as measured on quiet I/Os" from the title. Table note 2 was revised to remove "estimated SSO density over cycles." Table note 3 was deleted. The table note for Table 2-9 * Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Flash*Freeze Mode* to remove the sentence stating that values do not include I/O static contribution. The table note for Table 2-10 * Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Sleep Mode* was updated to remove VJTAG and VCCI and the statement that values do not include I/O static contribution. The table note for Table 2-11 * Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Shutdown Mode was updated to remove the statement that values do not include I/O static contribution. Note 2 of Table 2-12 * Quiescent Supply Current (IDD), No IGLOO PLUS Flash*Freeze Mode 1 was updated to include VCCPLL. Table note 4 was deleted.
2-2
2-3
2-7
2-7
2-8
2-8
Table 2-13 * Summary of I/O Input Buffer Power (per pin) - Default I/O Software 2-9, 2-9 Settings and Table 2-14 * Summary of I/O Output Buffer Power (per pin) - Default I/O Software Settings1 were updated to remove static power. The table notes were updated to reflect that power was measured on VCCI. Table note 2 was added to Table 2-13 * Summary of I/O Input Buffer Power (per pin) - Default I/O Software Settings. Table 2-16 * Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices and Table 2-18 * Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices were updated to change the definition for PDC5 from bank static power to bank quiescent power. Table subtitles were added for Table 2-16 * Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices, Table 2-17 * Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices, and Table 2-18 * Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices. The "Total Static Power Consumption--PSTAT" section was revised. Table 2-32 * Schmitt Trigger Input Hysteresis is new. Packaging v1.3 The "281-Pin CSP" package drawing is new. The "281-Pin CSP" table for the AGLP125 device is new. 2-11, 2-12
2-12 2-26 3-13 3-13
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IGLOO PLUS Low Power Flash FPGAs
Revision Revision 3 (continued)
Changes The "289-Pin CSP" package drawing was incorrect. The graphic was showing the CS281 mechanical drawing and not the CS289 mechanical drawing. This has now been corrected. The "289-Pin CSP" table for the AGLP030 device is new.
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Revision 2 (Jun 2008) Packaging v1.2 Revision 1 (Jun 2008) Packaging v1.1
3-17
The "289-Pin CSP" table for the AGLP060 device is new. The "289-Pin CSP" table for the AGLP125 device is new.
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4 -5
Datasheet Information
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "IGLOO PLUS Device" table on page II, is designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible.
Unmarked (production)
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States.
Actel Safety Critical, Life Support, and High-Reliability Applications Policy
The Actel products described in this advance status document may not have completed Actel's qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel's Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel's products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information.
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Actel is the leader in low power FPGAs and mixed signal FPGAs and offers the most comprehensive portfolio of system and power management solutions. Power Matters. Learn more at www.actel.com. Actel Corporation
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